CY28447 ETC, CY28447 Datasheet - Page 12

• Manufacturer Part Number: CY28447
• Description: Clock Generator
• Manufacturer: ETC

Rev 1.0, November 20, 2006
CPU_STP# Assertion
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable via assertion
of CPU_STP# will be stopped within two–six CPU clock
periods after being sampled by two rising edges of the internal
CPUC clock. The final states of the stopped CPU signals are
CPUT = HIGH and CPUC = LOW. There is no change to the
output drive current values during the stopped state. The
CPUC(Free Running
CPUT(Free Running
CPUC(Stoppable)
CPUT(Stoppable)
CPU_STOP#
CPUC Internal
CPUT Internal
CPU_STP#
CPU_STP#
DOT96C
DOT96T
CPUT
CPUC
CPUT
CPUC
PD
Figure 8. CPU_STP# = Driven, CPU_PD = Driven, DOT_PD = Driven
Figure 7. CPU_STP# Deassertion Waveform
Figure 6. CPU_STP# Assertion Waveform
Tdrive_CPU_STP#,10 ns>200 mV
CPUT is driven HIGH with a current value equal to 6 x (Iref),
and the CPUC signal will be tri-stated.
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner, synchronous manner meaning that no
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the deassertion to active
outputs is no more than two CPU clock cycles.
1.8 ms
CY28447
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