CY28447 ETC, CY28447 Datasheet - Page 14

• Manufacturer Part Number: CY28447
• Description: Clock Generator
• Manufacturer: ETC

Rev 1.0, November 20, 2006
PCI_STP# Deassertion
The deassertion of the PCI_STP# signal will cause all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transi-
tions to a HIGH level.
FS_A, FS_B,FS_C
VDD Clock Gen
VTT_PW RGD#
PW RGD_VRM
Clock Outputs
Clock State
Clock VCO
VDD_A = 2.0V
SRC 100MHz
PCI_STP#
Power Off
PCI_F
S0
PCI
State 0
Off
Off
0.2-0.3mS
Figure 11. PCI_STP# Deassertion Waveform
Figure 13. Single-ended Load Configuration
Tsu
State 1
Delay
Figure 12. VTT_PWRGD# Timing Diagram
VDD_A = off
Tdrive_SRC
>0.25mS
Delay
VTT_PW RGD#
S1
W ait for
On
VTT_PWRGD# = toggle
VTT_PWRGD# = Low
Operation
Normal
Sample Sels
State 2
S3
Inputs straps
On
State 3
Sample
Enable Outputs
S2
VTT_PW RGD# is ignored
Device is not affected,
Wait for <1.8ms
CY28447
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