CY28447 ETC, CY28447 Datasheet - Page 2

• Manufacturer Part Number: CY28447
• Description: Clock Generator
• Manufacturer: ETC

Rev 1.0, November 20, 2006
Pin Description
1, 49, 54, 65 VDD_SRC
2, 3, 50, 51,
52, 53, 55,
56, 58, 59,
60, 61, 63,
64, 66, 67,
69, 70
4, 68
5, 6
7
8
9
10, 11, 13, 14 CPUT/C[0:1]
12
15
16
17
18
19
20
21
22
23
24
25
26, 28, 29,
38, 46, 57,
62, 71, 72
27, 32, 33
30, 36
31, 35
34
37
Pin No.
SRCT/C[1:9]
VSS_SRC
CPUT2_ITP/SRCT10,
CPUC2_ITP/SRCC10
VDDA
VSSA
IREF
VDD_CPU
VSS_CPU
SCLK
SDATA
VDD_REF
XOUT
XIN
VSS_REF
REF1
REF0/FSC_TESTSEL I/O,PD Fixed 14.318 clock output / 3.3V-tolerant input for CPU frequency
CPU_STP#
PCI_STP#
CLKREQ[1:9]#
PCI[1:3]
VDD_PCI
VSS_PCI
PCI4/FCTSEL1
ITP_SEL/PCIF0
Name
I/O, OD SMBus-compatible SDATA.
I/O, PD,
I/O, PD 33 MHz clock output / 3.3V LVTTL input for selecting pins 47,48 (SRC[T/C]0,
O, DIF 100 MHz Differential serial reference clocks.
O, DIF Selectable differential CPU or SRC clock output.
O, DIF Differential CPU clock outputs.
O, SE 14.318 MHz crystal output.
O, SE 33 MHz clock outputs
PWR 3.3V power supply for outputs.
GND
PWR 3.3V power supply for PLL.
GND
PWR 3.3V power supply for outputs.
GND
PWR 3.3V power supply for outputs.
GND
I, PU
I, PU
PWR 3.3V power supply for outputs.
GND
I, PU
Type
SE
O
I
I
I
Ground for outputs.
ITP_SEL = 0 @ VTT_PWRGD# assertion = SRC10
ITP_SEL = 1 @ VTT_PWRGD# assertion = CPU2
Ground for PLL.
A precision resistor is attached to this pin which is connected to the internal
current reference.
Ground for outputs.
SMBus-compatible SCLOCK.
14.318 MHz crystal input.
Ground for outputs.
Fixed 14.318 MHz clock output.
selection/Selects test mode if pulled to V
asserted LOW.
Refer to DC Electrical Specifications table for V
cations.
3.3V LVTTL input for CPU_STP# active LOW.
3.3V LVTTL input for PCI_STP# active LOW.
3.3V LVTTL input for enabling assigned SRC clock (active LOW).
Ground for outputs.
100M[T/C]) and pins 43,44 (DOT96[T/C] and 27M Spread and Non-spread)
(sampled on the VTT_PWRGD# assertion).
3.3V LVTTL input to enable SRC10 or CPU2_ITP / 33-MHz clock output.
(sampled on the VTT_PWRGD# assertion).
1 = CPU2_ITP, 0 = SRC10
FCTS E L1 P in 43
0 DOT96T
1 27M_NSS
P in 44
DOT96C
27M_SS
Description
IMFS_C
ILFS_C
P in 47
96/100M_T 96/100M_C
SRCT0
when VTT_PWRGD# is
,V
IMFS_C
P in 48
SRCC0
CY28447
,V
Page 2 of 21
IHFS_C
specifi-