MT16LSDT1664AG-133B1 Micron, MT16LSDT1664AG-133B1 Datasheet - Page 12

• Manufacturer Part Number: MT16LSDT1664AG-133B1
• Description: DRAM Module, 64MB (x64, SR), 128MB (x64, DR) 168-PIN SDRAM UDIMM
• Manufacturer: Micron

Commands
able commands. This is followed by written descrip-
tion of each command. For a more detailed descrip-
Table 9:
NOTE:
pdf: 09005aef812230b2, source: 09005aef81037690
SD8_16C8_16x64AG.fm - Rev. C 7/04 EN
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0–A11 define the op-code written to the mode register.
3. A0–A11provide device row address, and BA0, BA1 determine which device bank is made active.
4. A0–A8 provide device column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW
5. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: all device banks are precharged and
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE
burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh
mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
The Truth Table provides a quick reference of avail-
disables the auto precharge feature; BA0, BA1 determine which device bank is being read from or written to.
BA0, BA1 are “Don’t Care.”
Truth Table – SDRAM Commands and DQMB Operation
NAME (FUNCTION)
CS#
H
L
L
L
L
L
L
L
L
–
–
12
RAS# CAS#
64MB (x64, SR), 128MB (x64, DR)
tion of commands and operations, refer to the 64Mb
SDRAM component data sheet.
X
H
H
H
H
L
L
L
L
–
–
Micron Technology, Inc., reserves the right to change products or specifications without notice.
H
H
H
H
X
L
L
L
L
–
–
WE#
168-PIN SDRAM UDIMM
H
H
H
H
X
L
L
L
L
–
–
DQMB
L/H
L/H
H
X
X
X
X
X
X
X
L
8
8
Bank/Row
Bank/Col
Bank/Col
Op-code
ADDR
Code
X
X
X
X
–
–
©2004 Micron Technology, Inc.
High-Z
Active
Active
Valid
DQ
X
X
X
X
X
X
X
NOTES
6, 7
3
4
4
5
2
8
8