MT16LSDT1664AG-133B1 Micron, MT16LSDT1664AG-133B1 Datasheet - Page 4

• Manufacturer Part Number: MT16LSDT1664AG-133B1
• Description: DRAM Module, 64MB (x64, SR), 128MB (x64, DR) 168-PIN SDRAM UDIMM
• Manufacturer: Micron

Table 6:
NOTE: Pin numbers may not correlate with symbols; refer to Pin Assignment tables page 3 for more information
pdf: 09005aef812230b2, source: 09005aef81037690
SD8_16C8_16x64AG.fm - Rev. C 7/04 EN
33, 34, 35, 36, 37, 38, 117, 118,
2–5, 7–11, 13–17, 19, 20, 55–
58, 60, 65–67, 69–72, 74–77,
104, 139–142, 144, 149–151,
86–89, 91–95, 97–101, 103,
112, 113, 130, 131
119, 120, 121, 123
153–156, 158–161
42, 79, 125, 163
30, 45, 114, 129
PIN NUMBERS
28, 29, 46, 47,
165, 166, 167
27, 111, 115
63, 128
39, 122
83
82
Pin Descriptions
RAS#, CAS#, WE#
DQMB0–DQMB7
SA0, SA1, SA2
CKE0, CKE1
DQ0–DQ63
SYMBOL
BA0, BA1
CK0–CK3
S0#–S3#
A0–A11
SDA
SCL
Output
Output
Input/
Input/
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
4
Command Inputs: RAS#, CAS#, and WE# (along with S#)
define the command being entered.
Clock: CK is driven by the system clock. All SDRAM input
signals are sampled on the positive edge of CK. CK also
increments the internal burst counter and controls the
output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW)
the CK signal. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all device
banks idle), ACTIVE POWER- DOWN (row ACTIVE in any
device bank) or CLOCK SUSPEND operation (burst access in
progress). CKE is synchronous except after the device enters
power- down and self refresh modes, where CKE becomes
asynchronous until after exiting the same mode. The input
buffers, including CK, are disabled during power-down and
self refresh modes, providing low standby power.
Chip Select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
Input/Output Mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-
clock latency) when DQMB is sampled HIGH during a READ
cycle.
Bank Address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address Inputs: Provide the row address for ACTIVE
commands, and the column addres and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines
whether the PRECHARGE applies to one device bank (A10
LOW, device bank selected by BA0, BA1) or all device banks
(A10 HIGH). The address input also provide the op-code
during a MODE REGISTER SET command.
Serial Clock for Presence-Detect: SCL is used to synchronize
the presence-detect data transfer to and from the module.
Serial Presence-Detect Data: SDA is a bidirectional pin used
to transfer addresses and data into and data out of the
presence-detect portion of the module.
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Data I/O: Data bus.
64MB (x64, SR), 128MB (x64, DR)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
168-PIN SDRAM UDIMM
DESCRIPTION
©2004 Micron Technology, Inc.