MT16LSDT1664AG-133B1 Micron, MT16LSDT1664AG-133B1 Datasheet - Page 21

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MT16LSDT1664AG-133B1

Manufacturer Part Number
MT16LSDT1664AG-133B1
Description
DRAM Module, 64MB (x64, SR), 128MB (x64, DR) 168-PIN SDRAM UDIMM
Manufacturer
Micron
Datasheet
Table 20: Serial Presence-Detect EEPROM DC Operating Conditions
V
Table 21: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to V
NOTE:
pdf: 09005aef812230b2, source: 09005aef81037690
SD8_16C8_16x64AG.fm - Rev. C 7/04 EN
1. To aviod spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
PARAMETER/CONDITION
PARAMETER/CONDITION
SUPPLY VOLTAGE
INPUT HIGH VOLTAGE: Logic 1; All inputs
INPUT LOW VOLTAGE: Logic 0; All inputs
OUTPUT LOW VOLTAGE: I
INPUT LEAKAGE CURRENT: V
OUTPUT LEAKAGE CURRENT: V
STANDBY CURRENT: SCL = SDA = V
POWER SUPPLY CURRENT:
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
DD
edge of SDA.
the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
= +3.3V ±0.3V; all voltages referenced to V
OUT
SS
= 3mA
IN
; V
= GND to V
OUT
DDSPD
= GND to V
DD
- 0.3V; All other inputs = V
= +3.3V ±0.3V
t
WRC) is the time from a valid stop condition of a write sequence to the end of
DD
DD
SS
21
SS
64MB (x64, SR), 128MB (x64, DR)
or V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
SYMBOL
t
t
t
t
t
HD:DAT
HD:STA
SU:DAT
SU:STA
SU:STO
t
t
t
t
HIGH
LOW
f
WRC
t
t
BUF
SCL
AA
DH
SYMBOL
t
t
I
t
I
F
R
CC
I
CC
V
V
I
V
I
V
CCS
Write
I
Read
LO
168-PIN SDRAM UDIMM
DD
OL
LI
IH
IL
MIN
200
100
V
0.2
1.3
0.6
0.6
1.3
0.6
0.6
0
DD
MIN
-10
-10
-1
3
x 0.7
MAX
300
400
0.9
0.3
50
10
V
V
DD
DD
UNITS
MAX
KHz
3.6
0.4
ms
10
10
30
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
ns
µs
µs
3
1
+ 0.5
x 0.3
©2004 Micron Technology, Inc.
NOTES
UNITS
mA
mA
µA
µA
µA
1
2
2
3
4
V
V
V
V

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