MT28F128J3FS-15F Micron, MT28F128J3FS-15F Datasheet - Page 24

• Manufacturer Part Number: MT28F128J3FS-15F
• Description: 128Mb Q-FLASH MEMORY
• Manufacturer: Micron

NOTE: 1. When the device is configured in one of the pulse modes, the STS pin pulses LOW with a typical pulse width of 250ns.
SET BLOCK LOCK BITS COMMAND
enabled via a combination of block lock bits. The block
lock bits gate PROGRAM and ERASE operations. Using
the SET BLOCK LOCK BITS command, individual block
lock bits can be set. This command is invalid when the
ISM is running or when the device is suspended. SET
BLOCK LOCK BITS commands are executed by a two-
cycle sequence. The set block lock bits setup, along
with appropriate block address, is followed by the set
block lock bits confirm and an address within the block
to be locked. The ISM then controls the set lock bit
algorithm. When the sequence is written, the device
automatically outputs status register data when read
(see Figure 9). The CPU can detect the completion of
the set block lock bit event by analyzing the STS pin
output or status register bit SR7. Upon completion of
128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_6.p65 – Rev. 5, Pub. 6/02
BITS 7–2
DQ7–DQ2 = Reserved
DQ1–DQ0 = STS Pin Configuration Codes
Configuration Codes 01b, 10b, and 11b are all pulse
modes such that the STS pin pulses LOW then HIGH
when the operation indicated by the given
configuration is completed.
Configuration command sequences for STS pin
configuration (masking bits DQ7–DQ2 to 00h) are as
follows:
A flexible block locking and unlocking scheme is
00 = Default, RY/BY# level mode
01 = Pulse on Erase Complete
10 = Pulse on Program Complete
11 = Pulse on Erase or Program Complete
Default RY/BY# level mode: B8h, 00h
ER INT (Erase Interrupt): B8h, 01h
PR INT (Program Interrupt): B8h, 02h
ER/PR INT (Erase or Program Interrupt): B8h, 03h
Pulse-on-Erase Complete
Pulse-on-Program Complete
Pulse-on-Erase or Program Complete
(device ready) indication
RESERVED
Configuration Coding Definitions
Table 17
24
PULSE ON
PROGRAM
COMPLETE
BIT 1
DQ7–DQ2 are reserved for future use.
Default RY/BY# level mode (DQ1–DQ0 = 00)
Configuration 01 ER INT, pulse mode
Configuration 10 PR INT, pulse mode
Configuration 11 ER/PR INT, pulse mode
set block lock bits operation, status register bit SR4
should be checked for error. If an error is detected, the
status register should be cleared. The CEL remains in
read status register mode until a new command is is-
sued. This two-step sequence of setup followed by ex-
ecution ensures that lock bits are not accidentally set.
An invalid SET BLOCK LOCK BITS command results in
status register bits SR4 and SR5 being set to “1.” Also,
reliable operation occurs only when V
valid. When V
against any data change.
ers can use the SECURE BLOCK LOCK command to the
specified block, or blocks on the device. If a SET BLOCK
LOCKS command is issued to a block that is already
locked, no error will be reported.
Used to control HOLD to a memory controller to
prevent accessing a Flash memory subsystem
while any Flash device’s ISM is busy.
Used to generate a system interrupt pulse when
any Flash device in an array has completed a
BLOCK ERASE or sequence of queued BLOCK
ERASEs; helpful for reformatting blocks after file
system free space reclamation or “cleanup.”
Used to generate a system interrupt pulse when
any Flash device in an array has completed a
PROGRAM operation. Provides highest perfor-
mance for enabling continuous BUFFER WRITE
operations.
Used to generate system interrupts to trigger
enabling of Flash arrays when either ERASE or
PROGRAM operations are completed and a
common interrupt service routine is desired.
For added protection on the MT28F320J3, design-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1
PEN
V
128Mb, 64Mb, 32Mb
PENLK
Q-FLASH MEMORY
, lock bit contents are protected
PULSE ON
COMPLETE
BIT 0
ERASE
PRELIMINARY
CC
1
©2002, Micron Technology, Inc.
and V
PEN
are