MT9080BPR Zarlink Semiconductor, Inc., MT9080BPR Datasheet - Page 11

• Manufacturer Part Number: MT9080BPR
• Description: SMX-Switch, SMX-Switch Matrix Module
• Manufacturer: Zarlink Semiconductor, Inc.

memory. The delay through the matrix can be
optimized for specific applications by selectively
enabling one of the two modes. Data Memory-1
(DM-1) is designed for voice switching applications
where it is generally desirable to minimize delay
through the switch. As mentioned earlier in the DM-1
description, the delay through the switch depends
upon the difference between the input channel
timeslot
Consecutive
non-contiguous input channels will not always
originate from the same input frame. For example, if
channels 3, 6 and 8 are to be switched to channels 5,
6 and 7; output channel 5 will contain data input in
the current frame, while channels 6 and 7 will contain
data clocked in one frame earlier. Data Memory-2
Note: All other inputs not shown in this diagram should be connected to GND.
Parallel Input Data
Generator
and
Timing
output
the
FP#1
FP#2
output
channels
CK
16
channel
Figure 15 - 1024 Channel Switch Matrix
switched
CK
FP
CD
D0
IRQ
FP
CK
i
-D15
D0
A0-A9
D0-D15
10
D0-D15
o
timeslot.
i
-D9
o
from
D10
ODE
R/W
R/W
CONNECTION
16-BIT MPU
MEMORY
o
MEMORY
SMX #1
SMX #2
DM-1/2
DATA
CM-1
(DM-2) is designed for data switching applications
where concatenation of a number of channels is
often necessary. Data clocked out of the device will
originate from the previous frame, regardless of the
input/output time difference. There is one exception,
when channel 1023 is switched to channel 0, the
contents of Channel 0 will not originate from the
previous frame but rather from the frame before it.
The capability to selectively change between DM-1
and DM-2 allows a single switch to handle both voice
and data effectively.
External bus drivers can be controlled with D13 of
the Connection Memory data bus.
output along with the remaining bits one channel
HALT
D11
DTA
ME
o
DS
DS
D12
Z
o
MODE
D0
MODE
A11-A15
A10-A15
Y
A0-A9
o
-D15
D13
A10
R/W
CS
CS
DS
X
X
Y
o
Z
o
CMOS
16
+5
0
1
0
+5
Parallel Output Data
Address
Decode
External
Tristate
Control
MT9080B
This bit will be
2-111