MT9080BPR Zarlink Semiconductor, Inc., MT9080BPR Datasheet - Page 12

• Manufacturer Part Number: MT9080BPR
• Description: SMX-Switch, SMX-Switch Matrix Module
• Manufacturer: Zarlink Semiconductor, Inc.

MT9080B
ahead of time; i.e., one channel before the
addressed data is clocked out of the Data Memory. It
may be necessary to provide an external bus enable
one channel ahead of time in applications where
precharging of the external data bus is required. In
other applications where no precharge is required,
control bit from the next channel may be used in
order to ensure that the external bus is enabled at
the same time as the channel is being clocked out of
the device.
2-112
CK
CONNECTION MEMORY TIMING
FP #2
Internal
Counter
(Read
Address)
Data Output
D0o-D15o
DATA MEMORY TIMING
Data Output
D0o-D15o
FP #1
Internal Counter
(Write Address)
Data In
D0i-D15i
Note 1: Address is latched into the Data Memory by the first positive clock edge in a timeslot (edge ➀ for Ch. 0). Data will be
Note 2: Data is latched into the Data Memory by the first rising edge in a timeslot (edge ➂ for Ch. 0) and is written into the
D15 - D14
clocked out by the first positive clock edge in the next timeslot (edge y for Ch. 0).
memory location addressed by the internal counter with the next rising edge (edge ➃ for Ch. 0).
Figure 17 - Mapping of Address and Control Signals onto Connect Memory Data Bits
Unused
1022
1023
CMOS
1021
External
Enable
Driver
1023
D13
1021
0
addresses
Figure 16 - 1024 Channel Switch Timing
1022
1021
1022
SMX #1 Data Input/Output Frame Boundary
➀
1
DM-1 or
0
Select
DM-2
D12
1023
1022
addresses
1023
y
2
The Change Detect (CD) output of the Connection
Memory is used to interrupt the MPU. As mentioned
in the Pin and Functional descriptions, CD goes low
when the internal CRC performed by the device
indicates a change in memory contents. This feature
is particularly useful in switching applications where
the Connection Memory is configured once and is
not modified for long periods of time, e.g., in network
digital
inadvertent corruption of the memory contents will
cause CD to interrupt the processor.
1
Message
Enable
D11
1023
0
access
➂
3
0
2
crossconnect
➃
1
0
Control
ODE
D10
1
3
4
1
2
systems.
Channel
Address
D9 - D0
Source
2
4
5
3
2
Any