MT9080BPR Zarlink Semiconductor, Inc., MT9080BPR Datasheet - Page 6

• Manufacturer Part Number: MT9080BPR
• Description: SMX-Switch, SMX-Switch Matrix Module
• Manufacturer: Zarlink Semiconductor, Inc.

MT9080B
2-106
Output
Timeslots
CK
Input
Data
CK
External
Address
Bus A0-A15
Data Output
D0-D15o
Address
generated by
Internal 11
Bit Counter
Data Input
D0-D15i
FP
Data on the input bus of the SMX is latched into the device with last rising edge of the clock within a timeslot. It is
written into the internal memory with the following positive edge.
Data is clocked out of the memory location and latched onto the output data bus with first positive clock edge in the
timeslot.
Switching channel 1 to channel 1 or channel 2 will result in one frame delay. Note that channel 2 is clocked out by CK
edge labelled ➀ while channel 1 is written into the memory with edge y. However, if channel 1 is switched to channel
3, there will be only one channel delay.
Data is clocked out of the memory location addressed by external address bus. The address is latched in with CK edge
marked ➀. Data is clocked out with CK edge marked y.
Data is latched into the device with the last rising edge of CK in the timeslot (e.g., edge ➂ in diagram). It is stored in the
memory location address by the internal 11 bit counter with the next rising clock edge (edge ➃ in diagram).
CH X
➀
CMOS
1
1022
Figure 5 - Throughput Delay in Data Memory Mode-1
Figure 4 - Data Memory Mode Functional Timing
1
➀
P
1023
CH Y
y
P
W
2
y
W
P
1023
P = Precharge
R = Read Memory
W = Write Memory
CH X
P = Precharge
R = Read Memory
W = Write Memory
R
P
2
R
CH Z
0
3
Counter Reset
0
CH Y
3
➂
1
4
➃
CH Z
1
4
2
5