MT90823AG Zarlink Semiconductor, Inc., MT90823AG Datasheet - Page 12

• Manufacturer Part Number: MT90823AG
• Description: Switch Fabric, 131.072Mbps Switching Bandwidth, 3.3V Supply Voltage, 120-PBGA
• Manufacturer: Zarlink Semiconductor, Inc.

MT90823
of the connection memory is transferred to the
ST-BUS outputs.
If the MC bit is low, the contents of the connection
memory stream address bit (SAB) and channel
address bit (CAB) defines the source information
(stream and channel) of the time-slot that will be
switched to the output.
Bit V/C (Variable/Constant Delay) of each connection
12
Notes:
1. Bit A7 must be high for access to data and connection memory positions. Bit A7 must be low for access to registers.
2. Channels 0 to 31 are used when serial interface is at 2Mb/s mode.
3. Channels 0 to 63 are used when serial interface is at 4Mb/s mode.
4. Channels 0 to 127 are used when serial interface is at 8Mb/s mode.
(Note 1)
OE bit in Connection
A7
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Memory
A6
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
CMOS
A5
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
1
.
Table 4 - Internal Register and Address Memory Mapping
A4
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
.
.
.
Don’t Care
ODE pin
Table 5 - Output High Impedance Control
0
0
1
A3
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
.
.
.
A2
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
.
.
.
OSB bit in IMS register
A1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
.
.
.
Don’t Care
Don’t care
memory location allows the per-channel selection
between variable and constant throughput delay
modes.
The loopback bit should be used for diagnostic
purpose only; this bit should be set to zero for normal
operation. If all LPBK bits are set high for all
connection
ST-BUS output channel data is internally looped
back to the ST-BUS input channel (i.e., SToN
channel m data loops back to STi N channel m).
0
1
A0
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
.
.
.
Control Register, CR
Interface Mode Selection Register, IMS
Frame Alignment Register, FAR
Frame Input Offset Register 0, FOR0
Frame Input Offset Register 1, FOR1
Frame Input Offset Register 2, FOR2
Frame Input Offset Register 3, FOR3
Ch 0
Ch 1
.
Ch 30
Ch 31
Ch 32
Ch 33
.
Ch 62
Ch 63
Ch 64
Ch 65
.
Ch 126
Ch 127
memory
ST-BUS Output Driver Status
locations,
High Impedance
High Impedance
Location
Per Channel
Enable
Enable
the
(Note 2)
(Note 3)
(Note 4)
associated