MT90823AG Zarlink Semiconductor, Inc., MT90823AG Datasheet - Page 5

• Manufacturer Part Number: MT90823AG
• Description: Switch Fabric, 131.072Mbps Switching Bandwidth, 3.3V Supply Voltage, 120-PBGA
• Manufacturer: Zarlink Semiconductor, Inc.

Pin Description (continued)
PLCC
41 -
84
36
37
38
39
40
48
49
50
MQFP
14-21
100
10
11
12
13
22
23
9
LQFP
11 -
100
Pin #
10
18
19
20
6
7
8
9
M8,N9,M9,N10
N6,M7,N7,N8,
BGA
M10
N11
120
M4
M5
M6
N4
N5
R/W / WR Read/Write / Write (5V Tolerant Input): In the cases of
RESET
A0 - A7
DS/RD
WFPS
Name
TRST
TCK
IC
Test Clock (5V Tolerant Input): Provides the clock to
the JTAG test logic.
Test Reset (3.3V Input with internal pull-up):
Asynchronously initializes the JTAG TAP controller by
putting it in the Test-Logic-Reset state. This pin should
be pulsed low on power-up, or held low, to ensure that
the MT90823 is in the normal functional mode.
Internal Connection (3.3V Input with internal
pull-down): Connect to V
pin must be low for the MT90823 to function normally
and to comply with IEEE 1149 (JTAG) boundary scan
requirements.
Device Reset (5V Tolerant Input): This input (active
LOW) puts the MT90823 in its reset state to clear the
device internal counters, registers and bring STo0 - 15
and microport data outputs to a high impedance state.
The time constant for a power up reset circuit must be a
minimum of five times the rise time of the power supply.
In normal operation, the RESET pin must be held low
for a minimum of 100nsec to reset the device.
Wide Frame Pulse Select (5V Tolerant Input): When
1, enables the wide frame pulse (WFP) Frame
Alignment interface. When 0, the device operates in
ST-BUS/GCI mode.
Address 0 - 7 (5V Tolerant Input): When
non-multiplexed CPU bus operation is selected, these
lines provide the A0 - A7 address lines to the internal
memories.
Data Strobe / Read (5V Tolerant Input): For Motorola
multiplexed bus operation, this input is DS. This active
high DS input works in conjunction with CS to enable
the read and write operations.
For Motorola non-multiplexed CPU bus operation, this
input is DS. This active low input works in conjunction
with CS to enable the read and write operations.
For multiplexed bus operation, this input is RD. This
active low input sets the data bus lines (AD0-AD7,
D8-D15) as outputs.
Motorola non-multiplexed and multiplexed bus
operations, this input is R/W. This input controls the
direction of the data bus lines (AD0 - AD7, D8-D15)
during a microprocessor access.
For multiplexed bus operation, this input is WR. This
active low input is used with RD to control the data bus
(AD0 - 7) lines as inputs.
Description
CMOS
SS
for normal operation. This
MT90823
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