MT90823AG Zarlink Semiconductor, Inc., MT90823AG Datasheet - Page 13

• Manufacturer Part Number: MT90823AG
• Description: Switch Fabric, 131.072Mbps Switching Bandwidth, 3.3V Supply Voltage, 120-PBGA
• Manufacturer: Zarlink Semiconductor, Inc.

If the LPBK bit is low, the loopback feature is
disabled. For proper per-channel loopback operation,
the contents of the frame delay offset registers must
be set to zero.
Initialization of the MT90823
During power up, the TRST pin should be pulsed low,
or held low continuously, to ensure that the MT90863
is in the normal functional mode. A 5K pull-down
resistor can be connected to this pin so that the
device will not enter the JTAG test mode during
power up.
Upon power up, the contents of the connection
memory can be in any state and the ODE pin should
be held low to keep all ST-BUS outputs in a high
impedance state until the microprocessor has
initialized the switching matrix.
15 - 6
3 - 0
Bit
5
4
15
0
Read/Write Address:
Reset Value:
Unused
14
STA3-0
Name
0
MBP
MS
13
0
Input/Output
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
Data Rate
12
Must be zero for normal operation.
Memory Block Program. When 1, the connection memory block programming
feature is ready for the programming of Connection Memory high bits, bit 11 to bit 15.
When 0, this feature is disabled.
Memory Select. When 0, connection memory is selected for read or write operations.
When 1, the data memory is selected for read operations and connection memory is
selected for write operations. (No microprocessor write operation is allowed for the
data memory.)
Stream Address Bits. The binary value expressed by these bits refers to the input or
output data stream, which corresponds to the subsection of memory made accessible
for subsequent operations. (STA3 = MSB, STA0 = LSB)
0
Table 7 - Valid Address lines for Different Bit Rates
11
0
00
0000
Table 6 - Control (CR) Register Bits
H
10
,
0
H
.
9
0
8
0
7
To prevent two ST-BUS outputs from driving the
same stream simultaneously, the microprocessor
should program the desired active paths through the
switch and put all other channels into a high
impedance state during the initialization routine by
using the block programming mode. In addition, the
loopback bits in the connection memory should be
cleared for normal operation.
When this process is complete, the microprocessor
controlling the matrices can bring the ODE pin or
OSB bit high to relinquish the high impedance state
control to the OE bit in the connection memory.
0
Description
6
0
MBP
5
A6, A5, A4 A3, A2, A1, A0
A5, A4, A3, A2, A1, A0
Valid Address Lines
A4, A3, A2, A1, A0
MS
4
CMOS
STA3
3
STA2
2
STA1
MT90823
1
STA0
0
13