MT90823AG Zarlink Semiconductor, Inc., MT90823AG Datasheet - Page 4

• Manufacturer Part Number: MT90823AG
• Description: Switch Fabric, 131.072Mbps Switching Bandwidth, 3.3V Supply Voltage, 120-PBGA
• Manufacturer: Zarlink Semiconductor, Inc.

MT90823
4
Pin Description
30, 54
64, 75
PLCC
1, 11,
2, 32,
3 - 10
12 -
84
63
27
28
29
31
33
34
35
31, 41,
56, 66,
MQFP
76, 99
68-75
81-96
5, 40,
100
100
67
97
98
6
7
8
LQFP
64,98
100
65 -
78 -
28,
38,
53,
63,
73,
37,
Pin #
96
72
93
94
95
97
CMOS
3
4
5
C1,C2,D1,D2,E1,
E2,F1,F2,G1,G2,
L3,L5,L7,L9,L11,
B6,A6,A5,B5,A4,
M2,M12,M13,N1
H1,H2,J1,J2,K1,
A1,A2,A12,A13,
D3,D11,F3,F11,
H3,H11,K3,K11,
C9,C11,E3,E11
C4,C6,C8,C10,
B13,C3,C5,C7,
G3,G11,J3,J11,
B1,B2,B7,B12,
L4,L6,L8,L10
B4,A3,B3
BGA
120
M3
K2
N1
N2
N3
L1
L2
STo8 - 15 ST-BUS Output 8 to 15 (5V Tolerant Three-state
FE/HCLK Frame Evaluation / HCLK Clock (5V Tolerant Input):
STi0 - 15 ST-BUS Input 0 to 15 (5V Tolerant Inputs): Serial
Name
TMS
TDO
CLK
V
V
TDI
F0i
DD
SS
Ground.
+3.3 Volt Power Supply.
Outputs): Serial data Output stream. These streams
may have data rates of 2.048, 4.096 or 8.192 Mb/s,
depending upon the value programmed at bits DR0 - 1
in the IMS register.
data input stream. These streams may have data rates
of 2.048, 4.096 or 8.192 Mb/s, depending upon the
value programmed at bits DR0 - 1 in the IMS register.
Frame Pulse (5V Tolerant Input): When the WFPS pin
is low, this input accepts and automatically identifies
frame synchronization signals formatted according to
ST-BUS and GCI specifications. When the WFPS pin is
high, this pin accepts a negative frame pulse which
conforms to WFPS formats.
When the WFPS pin is low, this pin is the frame
measurement input. When the WFPS pin is high, the
HCLK (4.096MHz clock) is required for frame alignment
in the wide frame pulse (WFP) mode.
Clock (5V Tolerant Input): Serial clock for shifting data
in/out on the serial streams (STi/o 0 - 15). Depending
upon the value programmed at bits DR0 - 1 in the IMS
register, this input accepts a 4.096, 8.192 or 16.384
MHz clock.
Test Mode Select (3.3V Input with internal pull-up):
JTAG signal that controls the TAP controller state
transitions.
Test Serial Data In (3.3V Tolerant Input with internal
pull-up): JTAG serial test instructions and data are
shifted in on this pin.
Test Serial Data Out (3.3V Output): JTAG serial data
is output on this pin on the falling edge of TCK. This pin
is held in high impedance state when JTAG scan is not
enabled.
Description