NT256D72S89AKGU Nanya Technology, NT256D72S89AKGU Datasheet - Page 3

• Manufacturer Part Number: NT256D72S89AKGU
• Description: 256MB DDR SDRAM DIMM
• Manufacturer: Nanya Technology

NT256D72S89AKGU
256MB : 32M x 72
Low Profile Registered DDR SDRAM DIMM
Input/Output Functional Description
REV 1.1
12/2002
RAS
DQS0 – DQS8
DQ0 – DQ63
DQ0 - DQ63
DM0 – DM8
CB0 – CB7
SA0 – SA2
BA0, BA1
A11, A12
V
V
A10/AP
Symbol
A0 - A9
RESET
,
DD,
CKE0
V
V
SDA
CK0
SCL
DDSPD
CK0
CAS
S0
DDQ
REF
V
SS
,
WE
(LVC-MOS)
(SSTL)
(SSTL)
(SSTL)
(SSTL)
(SSTL)
Supply
Supply
(SSTL)
(SSTL)
(SSTL)
(SSTL)
Supply
(SSTL)
Supply
Type
Input
Negative
Negative
Positive
Positive
Polarity
Active
Active
Active
Active
Active
Active
Edge
Edge
Edge
High
High
High
Low
Low
Low
and
-
-
-
-
-
-
The positive line of the differential pair of system clock inputs which drives the input to
the on-DIMM PLL. All the DDR SDRAM address and control inputs are sampled on the
rising edge of their associated clocks.
The negative line of the differential pair of system clock inputs which drives the input to
the on-DIMM PLL.
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh
mode.
Enables the associated SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new commands
are ignored but previous operations continue.
When sampled at the positive rising edge of the clock, RAS
operation to be executed by the SDRAM.
Reference voltage for SSTL-2 inputs
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9, A11 defines the column address
(CA0-CA10) when sampled at the rising clock edge. In addition to the column address,
AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write
cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be
precharged. If AP is low, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to
pre-charge.
Data and Check Bit input/output pins operate in the same manner as on conventional
DRAMs.
Data and Check Bit Input/Output pins. Check bits are only applicable on the x72 DIMM
configurations.
Power and ground for the DDR SDRAM input buffers and core logic
Data strobe for input and output data
The data write masks, associated with one data byte. In Write mode, DM operates as a
byte mask by allowing input data to be written if it is low but blocks the write operation if
it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits
CB0-CB7, and is not used on x64 modules.
Address inputs. Connected to either V
Serial Presence Detect EEPROM address.
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V
Serial EEPROM positive power supply.
3
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
DD
DD
Function
or V
to act as a pullup.
SS
DD
on the system board to configure the
to act as a pullup.
,
CAS
© NANYA TECHNOLOGY CORP.
,
WE define the