NT256D72S89AKGU Nanya Technology, NT256D72S89AKGU Datasheet - Page 13

• Manufacturer Part Number: NT256D72S89AKGU
• Description: 256MB DDR SDRAM DIMM
• Manufacturer: Nanya Technology

NT256D72S89AKGU
256MB : 32M x 72
Low Profile Registered DDR SDRAM DIMM
AC Timing Specification Notes
1. Input slew rate = 1V/ns.
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for
3. Inputs are not recognized as valid until V
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V
5. t
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid
8. A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device.
9. For command/address input slew rate >= 1.0 V/ns. Slew rate is measured between V
10. For command/address input slew rate >= 0.5 V/ns and < 1.0 V/ns. Slew rate is measured between V
11. CK/CK slew rates are >= 1.0 V/ns.
12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by
13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t CK is equal to the actual system
14. An input setup and hold time derating table is used to increase t IS and t IH in the case where the input slew rate is below 0.5 V/ns.
15. An input setup and hold time derating table is used to increase t DS and t DH in the case where the I/O slew rate is below 0.5 V/ns.
16. An I/O Delta Rise, Fall Derating table is used to increase t DS and t DH in the case where DQ, DM, and DQS slew rates differ.
REV 1.1
12/2002
1.
2.
1.
2.
1.
2.
3.
4.
signals other than CK/CK is V
specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
performance (bus turnaround) degrades accordingly.
transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in
progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW,
or transitioning from high to low at this time, depending on tDQSS.
HZ
design or tester characterization.
clock cycle time. For example, for PC2100 at CL= 2.5, t DAL = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5.
Delta Rise and Fall Rate
and t
Input slew rate is based on the lesser of the slew rates determined by either V
rising transitions.
These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
I/O slew rate is based on the lesser of the slew rates determined by either V
rising transitions.
These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
Input slew rate is based on the lesser of the slew rates determined by either V
rising transitions.
Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate.
The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)]
For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns. Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V
Using the table above, this would result in an increase in t
These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
Input Slew Rate
Input Slew Rate
LZ
0.25 ns/V
0.5 V/ns
0.4 V/ns
0.3 V/ns
0.5 V/ns
0.4 V/ns
0.3 V/ns
0.0 ns/V
0.5 ns/V
transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a
REF
.
REF
Delta (tDS
Delta (tDS
Delta (tIS
stabilizes.
+100
+150
+100
+50
+75
+50
0
0
0
)
)
)
DS
13
and t
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
DH
Delta (tDH
Delta (tDH
of 100 ps.
Delta (tIH
+150
+100
+75
+50
0
0
0
0
0
IH (AC)
IH (AC)
IH (AC)
)
)
)
OH
to V
(AC) and V
to V
to V
IL (AC)
IL (AC)
IL (AC)
or V
OL
or V
or V
OH
(AC).
IH (DC)
IH (DC)
IH (DC)
(AC) and V
Unit
Unit
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
© NANYA TECHNOLOGY CORP.
to V
to V
to V
IL (DC),
OL
IL (DC),
IL (DC),
(AC).
TT.
similarly for
similarly for
similarly for
Note
Note
Note
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1-4
1-4
1-4