RM5261-200-QI PMC-Sierra Inc, RM5261-200-QI Datasheet - Page 24

• Manufacturer Part Number: RM5261-200-QI
• Description: RM5261 Microprocessor with 64-Bit System Bus Data Sheet Released
• Manufacturer: PMC-Sierra Inc

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002241, Issue 1
3.27 External Requests
3.28 Interrupt Handling
3.29 Standby Mode
3.30 JTAG Interface
3.31 Boot-Time Options
In write reissue mode, a write rate of one write every two bus cycles can be achieved. Pipelined
writes have the same two bus cycle write repeat rate, but can issue one additional write following
the deassertion of WrRdy*.
The External Request pin, ExtRqst*, is asserted by the external agent when it requires mastership
of the system interface, either to perform an independent transfer or to write to the interrupt
register within the RM5261. An independent transfer is a data transfer between two external
agents or between an external agent and the memory or peripheral on the system interface.
Following the assertion of ExtRqst*, the RM5261 tri-states its drivers allowing the external agent
to use the system interface buses to complete an independent transfer. The external agent is
responsible for returning mastership of the system interface to the RM5231 when it has completed
the independent transfer and does so by executing an External Null cycle.
The RM5261 supports a dedicated interrupt vector. When enabled by the real time executive (by
setting a bit in the Cause register), interrupts vector to a specific address that is not shared with any
of the other exception types. This capability eliminates the need to go through the normal software
routine for exception decode and dispatch, thereby lowering interrupt latency.
The RM5261 provides a means to reduce the amount of power consumed by the internal core
when the CPU would otherwise not be performing any useful operations. This state is known as
Standby Mode.
Executing the WAIT instruction enables interrupts and causes the processor to enter Standby
Mode. When the wait instruction completes the W pipe stage, and if the SysAD bus is currently
idle, the internal processor clock stops, thereby freezing the pipeline. The phase lock loop, or PLL,
internal timer/counter, and the “wake up” input pins: Int[5:0]*, NMI*, ExtReq*, Reset*, and
ColdReset* will continue to operate in their normal fashion. If the SysAD bus is not idle when the
WAIT instruction completes the W pipe-stage, then the WAIT is treated as a NOP until the bus
operation is completed. Once the processor is in Standby, any interrupt, including the internally
generated timer interrupt, causes the processor to exit Standby mode and resume operation where
it left off. The WAIT instruction is typically inserted in the idle loop of the operating system or real
time executive.
The RM5261 interface supports JTAG Test Access Port (TAP) boundary scan in conformance with
the IEEE 1149.1 specification. The JTAG interface is especially helpful for checking the integrity
of the processors pin connections.
Fundamental operational modes for the processor are initialized by the boot-time mode control
interface. This serial interface operates at a very low frequency (SysClock divided by 256). The
low frequency operation allows the initialization information to be kept in a low cost EPROM or
system interface ASIC.
RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
Released
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