RM5261-200-QI PMC-Sierra Inc, RM5261-200-QI Datasheet - Page 5

• Manufacturer Part Number: RM5261-200-QI
• Description: RM5261 Microprocessor with 64-Bit System Bus Data Sheet Released
• Manufacturer: PMC-Sierra Inc

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002241, Issue 1
Table of Contents
Legal Information ...........................................................................................................................2
Revision History .............................................................................................................................3
Document Conventions .................................................................................................................4
Table of Contents ..........................................................................................................................5
List of Figures ................................................................................................................................7
List of Tables .................................................................................................................................8
1
2
3
Features ..................................................................................................................................9
Block Diagram .......................................................................................................................10
Hardware Overview ...............................................................................................................11
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10 Floating-Point General Register File ............................................................................15
3.11 System Control Co-processor (CP0) ............................................................................15
3.12 System Control Co-Processor Registers .....................................................................15
3.13 Virtual to Physical Address Mapping ............................................................................16
3.14 Joint TLB ......................................................................................................................17
3.15 Instruction TLB .............................................................................................................18
3.16 Data TLB ......................................................................................................................18
3.17 Cache Memory .............................................................................................................18
3.18 Instruction Cache .........................................................................................................19
3.19 Data Cache ..................................................................................................................19
3.20 Write buffer ..................................................................................................................21
3.21 System Interface ..........................................................................................................21
3.22 System Address/Data Bus ...........................................................................................21
3.23 System Command Bus ................................................................................................21
3.24 Handshake Signals ......................................................................................................22
3.25 Non-overlapping System Interface ...............................................................................22
3.26 Enhanced Write Modes ................................................................................................23
3.27 External Requests ........................................................................................................24
3.28 Interrupt Handling ........................................................................................................24
3.29 Standby Mode ..............................................................................................................24
3.30 JTAG Interface .............................................................................................................24
Superscalar Dispatch ...................................................................................................11
CPU Registers .............................................................................................................11
Integer Unit ..................................................................................................................11
Pipeline ........................................................................................................................12
Register File .................................................................................................................12
ALU ..............................................................................................................................12
Integer Multiply/Divide ..................................................................................................13
Floating-Point Co-Processor ........................................................................................13
Floating-Point Unit .......................................................................................................13
RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
Released
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