cy28549 SpectraLinear Inc, cy28549 Datasheet - Page 12

• Manufacturer Part Number: cy28549
• Description: Clock Generator For Intel Ck410m
• Manufacturer: SpectraLinear Inc

Document #:xxx-xxxxx Rev **
controlled by CLKREQ# are determined by the settings in
register byte 8. The CLKREQ# signal is a de-bounced signal
in that it’s state must remain unchanged during two consec-
utive rising edges of SRCC to be recognized as a valid
assertion or deassertion. (The assertion and deassertion of
this signal is absolutely asynchronous.)
CLK_REQ[1:9]# Assertion (CLKREQ# -> LOW)
All differential outputs that were stopped are to resume normal
operation in a glitch-free manner. The maximum latency from
the assertion to active outputs is between 2 and 6 SRC clock
periods (2 clocks are shown) with all SRC outputs resuming
simultaneously. All stopped SRC outputs must be driven HIGH
within 10 ns of CLKREQ# deassertion to a voltage greater than
200 mV.
CLK_REQ[1:9]# Deassertion (CLKREQ# -> HIGH)
The impact of deasserting the CLKREQ# pins is that all SRC
outputs that are set in the control registers to stoppable via
deassertion of CLKREQ# are to be stopped after their next
transition. The final state of all stopped SRC clocks is
Low/Low.
PD (Power-down) Clarification
The VTT_PWRGD#/PD pin is a dual-function pin. During initial
power-up, the pin functions as VTT_PWRGD#. Once
VTT_PWRGD# has been sampled LOW by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
active HIGH input used to shut off all clocks cleanly prior to
SRCC(free running)
SRCT(free running)
SRCT(stoppable)
SRCT(stoppable)
CPUC, 133MHz
CPUT, 133MHz
CLKREQ#X
SRCC 100MHz
SRCT 100MHz
PCI, 33 MHz
USB, 48MHz
DOT96C
DOT96T
REF
PD
Figure 3. CLK_REQ#[1:9] Deassertion/Assertion Waveform
Figure 4. Power-down Assertion Timing Waveform
PRELIMINARY
shutting off power to the device. This signal is synchronized
internal to the device prior to powering down the clock synthe-
sizer. PD is also an asynchronous input for powering up the
system. When PD is asserted HIGH, all clocks need to be
driven to a LOW value and held prior to turning off the VCOs
and the crystal oscillator.
PD (Power-down) Assertion
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs will be held LOW on their
next HIGH-to-LOW transition and differential clocks must be
held HIGH or tri-stated (depending on the state of the control
register drive mode bit) on the next diff clock# HIGH-to-LOW
transition within 4 clock periods. When the SMBus PD drive
mode bit corresponding to the differential (CPU, SRC, and
DOT) clock output of interest is programmed to ‘0’, the clock
outputs are held with “Diff clock” pin driven HIGH, and “Diff
clock#” tri-state. If the control register PD drive mode bit corre-
sponding to the output of interest is programmed to “1”, then
both the “Diff clock” and the “Diff clock#” are tri-state. Note that
Figure 4 shows CPUT = 133 MHz and PD drive mode = ‘1’ for
all differential outputs. This diagram and description is appli-
cable to valid CPU frequencies 100, 133, 166, and 200 MHz.
In the event that PD mode is desired as the initial power-on
state, PD must be asserted HIGH in less than 10 μs after
asserting Vtt_PwrGd#. It should be noted that 96_100_SSC
will follow the DOT waveform when selected for 96 MHz and
the SRC waveform when in 100-MHz mode.
CY28549
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