cy28549 SpectraLinear Inc, cy28549 Datasheet - Page 13

• Manufacturer Part Number: cy28549
• Description: Clock Generator For Intel Ck410m
• Manufacturer: SpectraLinear Inc

Document #:xxx-xxxxx Rev **
PD Deassertion
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD pin or the ramping of the power
supply until the time that stable clocks are output from the
clock chip. All differential outputs stopped in a three-state
condition resulting from power down will be driven high in less
CPU_STP# Assertion
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
CPUC Internal
CPUT Internal
CPU_STP#
CPU_STP#
CPUT
CPUC
CPUT
CPUC
CPUC, 133MHz
CPUT, 133MHz
SRCC 100MHz
SRCT 100MHz
USB, 48MHz
PCI, 33MHz
DOT96C
DOT96T
REF
Figure 5. Power-down Deassertion Timing Waveform
PD
Figure 7. CPU_STP# Deassertion Waveform
Figure 6. CPU_STP# Assertion Waveform
Tdrive_CPU_STP#,10 ns>200 mV
PRELIMINARY
<300 μs, >200 mV
Tdrive_PWRDN#
<1.8 ms
Tstable
than 300 μs of PD deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs will be enabled within a few clock cycles of
each other. Figure 5 is an example showing the relationship of
clocks coming up. It should be noted that 96_100_SSC will
follow the DOT waveform when selected for 96 MHz and the
SRC waveform when in 100-MHz mode.
set with the SMBus configuration to be stoppable via assertion
of CPU_STP# will be stopped within two–six CPU clock
periods after being sampled by two rising edges of the internal
CPUC clock. The final state of all stopped CPU clocks is
High/Low when driven, Low/Low when tri-stated.
CY28549
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