cy28549 SpectraLinear Inc, cy28549 Datasheet - Page 7

• Manufacturer Part Number: cy28549
• Description: Clock Generator For Intel Ck410m
• Manufacturer: SpectraLinear Inc

Document #:xxx-xxxxx Rev **
Byte 3 Control Register 3
Byte 4 Control Register 4
Byte 5 Control Register 5
Byte 6 Control Register 6
Bit
Bit
7
6
5
4
3
2
1
0
7
6
Bit
Bit
5
4
3
2
1
0
4
3
2
1
0
7
6
@Pup
@Pup
0
0
0
0
0
1
1
1
0
0
@Pup
@Pup
1
1
1
1
1
0
0
0
0
0
0
0
0
LCD_96_100M[T/C]
CPU[T/C]2/SRC[T/C]10 CPU[T/C]2/SRC[T/C]10 Output Enable
DOT96[T/C]
RESERVED
RESERVED
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
CPU[T/C]2
SRC[T/C]
RESERVED
RESERVED
RESERVED
PCIF0
Name
Name
Name
Name
SRC7
SRC6
SRC5
SRC4
SRC3
SRC2
SRC1
SRC0
PCI1
PRELIMINARY
LCD_96_100M[T/C] PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
DOT PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
RESERVED, Set = 0
RESERVED, Set = 0
Allow control of PCIF0 with assertion of SW and HW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of CPU[T/C]2 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Allow control of CPU[T/C]1 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Allow control of CPU[T/C]0 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
SRC[T/C] Stop Drive Mode
0 = Driven when PCI_STP# asserted
1 = Tri-state when PCI_STP# asserted
CPU[T/C]2 Stop Drive Mode
0 = Driven when CPU_STP# asserted
1 = Tri-state when CPU_STP# asserted
PCI1 Output Enable
0 = Disabled, 1 = Enabled
RESERVED
RESERVED
0 = Disabled, 1 = Enabled
RESERVED
Allow control of SRC[T/C]7 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]6 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]5 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]4 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]3 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]2 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]1 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]0 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Description
Description
Description
Description
CY28549
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