cy28549 SpectraLinear Inc, cy28549 Datasheet - Page 4

• Manufacturer Part Number: cy28549
• Description: Clock Generator For Intel Ck410m
• Manufacturer: SpectraLinear Inc

Document #:xxx-xxxxx Rev **
Pin Description
Frequency Select Pins (FSA, FSB, and FSC)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FSA, FSB, FSC inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled LOW by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FSA, FSB, and FSC input values. For all logic
levels of FSA, FSB, and FSC, VTT_PWRGD# employs a
one-shot functionality in that once a valid LOW on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FSA, FSB, and FSC transitions will be ignored, except in test
mode.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
Table 2. Frequency Select Table FSA, FSB, and FSC
Table 3. Command Code Definition
Table 4. Block Read and Block Write Protocol
62
63
64
65
66
67
68
69
70
71
72
FSC
1
0
0
0
Pin No.
(6:0)
8:2
Bit
Bit
1
9
7
FSB
0
0
1
1
Start
Slave address–7 bits
Write
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
SRCC_5
CLKREQ6#
SRCT_6
SRCC_6
VDD_SRC
SRCT_7
SRCC_7
VSS_SRC
SRCC_8
SRCT_8
CLKREQ8#
FSA
1
1
1
0
(continued)
Block Write Protocol
Name
100 MHz
133 MHz
166 MHz
200 MHz
CPU
Description
O, DIF Complementary 100-MHz Differential serial reference clocks.
O, DIF True 100-MHz Differential serial reference clocks.
O, DIF Complementary 100-MHz Differential serial reference clocks.
O, DIF True 100-MHz Differential serial reference clocks.
O, DIF Complementary 100-MHz Differential serial reference clocks.
O, DIF Complementary 100-MHz Differential serial reference clocks.
O, DIF True 100-MHz Differential serial reference clocks.
PWR 3.3V power supply for outputs.
GND
Type
100 MHz
100 MHz
100 MHz
100 MHz
I
I
SRC
3.3V LVTTL input for enabling assigned SRC clock (active LOW).
3.3V LVTTL input for enabling assigned SRC clock (active LOW).
Ground for outputs.
PRELIMINARY
PCIF/PCI
33 MHz
33 MHz
33 MHz
33 MHz
Description
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 3.
The block write and block read protocol is outlined in Table 4
while Table 5 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h)
Bit
8:2
1
9
27 MHz
27 MHz
27 MHz
27 MHz
27MHz
Start
Slave address–7 bits
Write
Description
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
Block Read Protocol
REF
Description
96 MHz
96 MHz
96 MHz
96 MHz
DOT96
CY28549
Page 4 of 23
48 MHz
48 MHz
48 MHz
48 MHz
USB