upd70208h Renesas Electronics Corporation., upd70208h Datasheet - Page 25

• Manufacturer Part Number: upd70208h
• Description: V40hltm, V50hltm 16/8, 16-bit Microprocessor
• Manufacturer: Renesas Electronics Corporation.

6. BAU (BUS ARBITRATION UNIT)
the end of the bus cycle currently being executed, as shown in Figure 6-1. However, in the case of a bus master connected
to the HLDRQ pin, or cascaded external DMA controllers, for instance, the situation is as shown in Figure 6-2. The V40HL
and V50HL request return of the bus by inactivating the acknowledge signal (HLDAK), and on receiving this request, the
external bus master holding the bus should release the bus by dropping the bus hold request signal (HLDRQ). The V40HL
and V50HL-internal bus master with the highest priority is kept waiting until the bus hold request signal is dropped. This
is called a bus wait operation.
The BAU performs bus arbitration among bus masters.
A list of bus masters (units which can acquire the bus) is shown below.
The relative priorities of the bus masters are shown below.
BAU bus arbitration is performed as follows.
A bus master such as the CPU, DMAU, REFU, etc., incorporated in the V40HL and V50HL normally release the bus at
High
Low
CPU (when BUSLOCK prefix is used)
REFU (highest priority: when given number of requests are reached)
DMAU
HLDRQ pin
CPU (normal CPU cycle)
REFU (lowest priority: cycle steal)
CPU
DMAU
REFU
External bus master
(HLDRQ pin input)
Bus Master
Data Sheet U13225EJ4V0DS00
Table 6-1. Bus Masters
Program fetch, data read/write
DMA cycle
Refresh cycle
Bus cycle driven by external device
Bus Cycle
PD70208H, 70216H
25