upd70208h Renesas Electronics Corporation., upd70208h Datasheet - Page 77

• Manufacturer Part Number: upd70208h
• Description: V40hltm, V50hltm 16/8, 16-bit Microprocessor
• Manufacturer: Renesas Electronics Corporation.

AC CHARACTERISTICS
(1)
External clock input cycle
External clock input high-level width (V
External clock input low-level width (V
External clock input rise time (0.2 V
External clock input fall time (0.8 V
Clock output cycle
Clock output high-level width (V
Clock output low-level width (V
Clock output rise time (0.2 V
Clock output fall time (0.7 V
CLKOUT delay time (vs. external clock)
Input rise time (except external clock) (0.2 V
Input fall time (except external clock) (0.7 V
Output rise time (except CLKOUT) (0.2 V
Output fall time (except CLKOUT) (0.7 V
RESET setup time (vs. CLKOUT )
RESET hold time (vs. CLKOUT )
RESOUT output delay time (vs. CLKOUT )
READY inactive setup time (vs. CLKOUT )
READY inactive hold time (vs. CLKOUT )
READY active setup time (vs. CLKOUT )
READY active hold time (vs. CLKOUT )
NMI setup time (vs. CLKOUT )
POLL setup time (vs. CLKOUT )
Data setup time (vs. CLKOUT )
Data hold time (vs. CLKOUT )
CLKOUT
CLKOUT
CLKOUT
CLKOUT
Address setup time (vs. ASTB )
CLKOUT
CLKOUT
CLKOUT
ASTB high-level width
Notes 1. When reset with the minimum pulse width or when guaranteeing the RESOUT output timing.
PD70208H, 70216H-10/12/16 (T
2. Specifications also corresponding to the QS0, QS1, and BUSLOCK signals, and A16/PS0-A19/PS3, UBE,
3. Specifications also corresponding to the A16/PS0-A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR,
address delay time
address hold time
PS delay time
PS float delay time
address float delay time
ASTB delay time
ASTB delay time
BUFEN, BUFR/W, MRD, IORD, MWR, IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing.
IOWR, and BS0-BS2 signals at HLDRQ/HLDAK timing.
Parameter
DD
DD
OL
Note 2
OH
0.2 V
=0.2 V
0.7 V
Note 1
=0.7 V
Note 1
DD
DD
DD
Note 3
KL
DD
KH
0.2 V
DD
)
=0.2 V
0.8 V
)
DD
DD
DD
=0.8 V
DD
A
)
DD
)
= –40 to +85 C, V
DD
0.7 V
0.2 V
DD
0.7 V
0.2 V
DD
)
)
DD
)
)
DD
DD
DD
DD
Data Sheet U13225EJ4V0DS00
)
)
)
)
<10>
<11>
<12>
<13>
<14>
<15>
<16>
<17>
<18>
<19>
<20>
<21>
<22>
<23>
<24>
<25>
<26>
<27>
<28>
<29>
<30>
<31>
<32>
<33>
<34>
<35>
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CYX
XXH
XXL
XR
XF
CYK
KKH
KKL
KR
KF
DXK
IR
IF
OR
OF
SRESK
HKRES
DKRES
SRYLK
HKRYL
SRYHK
HKRYH
SNMIK
SPOLK
SDK
HKD
DKA
HKA
DKP
FKP
SAST
FKA
DKSTH
DKSTL
STST
DD
= 3 V 10%) (1/3)
0.5t
0.5t
t
t
MIN.
KKL
KKL
PD70208H-10
PD70216H-10
100
200
40
40
25
35
20
30
20
30
15
20
20
CYK
CYK
5
5
5
5
5
5
5
5
5
–30
–10
–7
–7
MAX.
DC
DC
10
10
75
20
12
20
12
80
75
80
80
80
65
70
7
7
0.5t
0.5t
t
t
KKL
KKL
PD70208H-12
PD70216H-12
MIN.
Output Pin Load Capacitance: C
166
83
30
30
25
35
20
30
20
30
15
20
20
CYK
CYK
5
5
5
5
5
5
5
5
5
–30
–10
–7
–7
PD70208H, 70216H
MAX.
DC
DC
10
10
65
20
12
20
12
70
65
70
70
70
55
60
7
7
0.5t
0.5t
t
t
KKL
KKL
PD70208H-16
PD70216H-16
MIN.
62.5
125
20
20
25
35
15
25
15
25
15
20
15
CYK
CYK
5
5
5
5
5
5
5
5
5
–30
–10
–7
–7
MAX.
DC
DC
10
10
55
20
12
20
12
60
55
60
60
60
45
50
7
7
L
= 100 pF
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
77