74HC74PW,118 NXP Semiconductors, 74HC74PW,118 Datasheet - Page 12
![IC DUAL POS-EDG-TRG D FF 14TSSOP](/photos/6/58/65814/568-14-tssop_sot402-1_sml.jpg)
74HC74PW,118
Manufacturer Part Number
74HC74PW,118
Description
IC DUAL POS-EDG-TRG D FF 14TSSOP
Manufacturer
NXP Semiconductors
Series
74HCr
Type
D-Typer
Datasheet
1.74HC74BQ115.pdf
(22 pages)
Specifications of 74HC74PW,118
Output Type
Differential
Package / Case
14-TSSOP
Function
Set(Preset) and Reset
Number Of Elements
2
Number Of Bits Per Element
1
Frequency - Clock
82MHz
Delay Time - Propagation
14ns
Trigger Type
Positive Edge
Current - Output High, Low
5.2mA, 5.2mA
Voltage - Supply
2 V ~ 6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Number Of Circuits
2
Logic Family
HC
Logic Type
D-Type Edge Triggered Flip-Flop
Polarity
Inverting/Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
14 ns at 5 V
High Level Output Current
- 5.2 mA
Low Level Output Current
5.2 mA
Supply Voltage (max)
6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Supply Voltage (min)
2 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-4574-2
74HC74PW-T
74HC74PW-T
935175130118
74HC74PW-T
74HC74PW-T
935175130118
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
74HC74PW,118
Manufacturer:
NXP Semiconductors
Quantity:
1 950
Philips Semiconductors
Family 74HCT
GND = 0 V; t
2003 Jul 10
T
t
t
t
t
t
t
f
T
t
t
t
t
t
t
f
PHL
THL
W
rem
su
h
max
PHL
THL
W
rem
su
h
max
amb
amb
Dual D-type flip-flop with set and reset;
positive-edge trigger
SYMBOL
/t
/t
/t
/t
TLH
TLH
PLH
PLH
= 40 to +85 C
= 40 to +125 C
r
= t
propagation
delay nCP to nQ, nQ
propagation
delay nSD to nQ, nQ
propagation
delay nRD to nQ, nQ
output transition time
clock pulse width HIGH
or LOW
set or reset pulse width
LOW
removal time set or
reset
set-up time nD to nCP
hold time nCP to nD
maximum clock pulse
frequency
propagation
delay nCP to nQ, nQ
propagation
delay nSD to nQ, nQ
propagation
delay nRD to nQ, nQ
output transition time
clock pulse width HIGH
or LOW
set or reset pulse width
LOW
removal time set or
reset
set-up time nD to nCP
hold time nCP to nD
maximum clock pulse
frequency
f
= 6 ns; C
PARAMETER
L
= 50 pF.
see Fig.7
see Fig.8
see Fig.8
see Fig.7
see Fig.7
see Fig.8
see Fig.8
see Fig.7
see Fig.7
see Fig.7
see Fig.7
see Fig.8
see Fig.8
see Fig.7
see Fig.7
see Fig.8
see Fig.8
see Fig.7
see Fig.7
see Fig.7
WAVEFORMS
TEST CONDITIONS
12
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
V
CC
(V)
23
20
8
15
+3
22
27
24
9
18
3
18
MIN.
74HC74; 74HCT74
18
23
24
7
9
9
1
5
54
3
TYP.
Product specification
44
50
50
19
53
60
60
22
MAX.
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
UNIT