si5315 Silicon Laboratories, si5315 Datasheet - Page 14

• Manufacturer Part Number: si5315
• Description: Synchronous Ethernet/telecom Jitter Attenuating Clock Multiplier
• Manufacturer: Silicon Laboratories

Table 4. Jitter Generation
(V
Jitter Gen OC-192
Jitter Gen OC-48
IEEE 802.3 GbE
RMS Jitter
Notes:
Si5315
14
DD
1. BWSEL [1:0] loop bandwidth settings provided in Table 7 on page 21.
2. 40 MHz fundamental mode crystal used as XA/XB input.
3. V
4. T
5. Si5315A test condition: f
6. Si5315B test condition: f
= 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T
Parameter
time (20–80%), LVPECL clock output.
80%), LVPECL clock output.
A
DD
= 85 °C
= 2.5 V
Symbol
J
J
J
GEN
GEN
GEN
IN
IN
Measurement
= 19.44 MHz, f
=19.44 MHz, f
Filter (MHz)
0.012–20
1.875–20
0.02–80
0.05–80
Test Condition
4–80
A
= –40 to 85 ºC)
OUT
OUT
DSPLL BW
= 125 MHz, LVPECL clock input: 1.19 Vppd with 0.5 ns rise/fall time (20-
= 161.1328125 MHz, LVPECL clock input: 1.19 Vppd with 0.5 ns rise/fall
Preliminary Rev. 0.2
113 Hz
113 Hz
113 Hz
113 Hz
111 Hz
83 Hz
1,2,3,4
6
5
5
5
5
6
1
Min
—
—
—
—
—
—
—
—
—
—
—
—
0.588
0.513
0.569
0.551
0.662
0.789
TBD
TBD
TBD
TBD
TBD
TBD
Typ
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
30 ps pp/0.3 UI
10 ps pp/0.1 UI
10 ps pp/0.1 UI
GR-253 Spec
(0.01 UI
40.2 ps pp/
(0.01 UI
40.2 ps pp/
(0.01 UI
4.02 ps
4.02 ps
(0.1 UIpp)
(0.1 UIpp)
1.0 ps
N/A
N/A
N/A
N/A
rms
rms
rms
rms
rms
rms
pp
pp
pp
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Unit
rms
rms
rms
rms
rms
rms
PP
PP
PP
PP
PP
PP