si5315 Silicon Laboratories, si5315 Datasheet - Page 36

• Manufacturer Part Number: si5315
• Description: Synchronous Ethernet/telecom Jitter Attenuating Clock Multiplier
• Manufacturer: Silicon Laboratories

Si5315
4.6. PLL Bypass Mode
The Si5315 supports a PLL bypass mode in which the selected input clock is fed directly to both enabled output
buffers, bypassing the DSPLL. Internally, the bypass path is implemented with high-speed differential signaling for
low jitter. In PLL bypass mode, the input and output clocks will be at the same frequency. PLL bypass mode is
useful in a laboratory environment to measure system performance with and without the jitter attenuation provided
by the DSPLL. The DSBL2_BY pin is used to select the PLL Bypass Mode according to Table 14.
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FRQSEL[3:0]
BWSEL[1:0]
AUTOSEL
FRQTBL
CKIN1+
CKIN1–
CKIN2+
CKIN2–
CS/CA
LOS1
LOS2
LOL
RST
2
2
Signal Detect
DSBL2/BYPASS
Bandwidth
Frequency
Control
Control
Control
M
H
L
Table 14. DSBL2/BYPASS Pin Settings
0
1
Xtal/Clock
f
3
Figure 9. Bypass Signal
XB
Preliminary Rev. 0.2
Reference Clock
PLL Bypass Mode w/ CKOUT2 Enabled
Crystal or
DSPLL
®
CKOUT2 Disabled
CKOUT2 Enabled
XA
PLL Bypass
Function
f
OSC
0
0
1
1
2
2
VDD (1.8, 2.5, or 3.3 V)
GND
DBL2_BY
CKOUT1+
CKOUT1–
SFOUT[1:0]
CKOUT2+
CKOUT2–