si5315 Silicon Laboratories, si5315 Datasheet - Page 45

• Manufacturer Part Number: si5315
• Description: Synchronous Ethernet/telecom Jitter Attenuating Clock Multiplier
• Manufacturer: Silicon Laboratories

8. Typical Phase Noise Plots
The following is a typical phase noise plot. The clock input source was a Rohde and Schwarz model SML03 RF
Generator. The spectrum analyzer was either an Agilent model E4400A or an Agilent model JS-500. The Si5315
operates at 3.3 V with an ac coupled differential PECL output and an ac coupled differential sine wave input from
the RF generator at 0 dBm. Note that, as with any PLL, the output jitter that is below the loop BW is caused by the
jitter at the input clock, not the Si5315. Except as noted, loop BWs of 60 Hz to 100 Hz were in use.
8.1. Example: 10G LAN SyncE
-100
-120
-140
-160
-20
-40
-60
-80
0
100
Brick Wall, 100 Hz to 100 MHz
SONET_OC48, 12 kHz to 20 MHz
SONET_OC192_A, 20 kHz to 80 MHz
SONET_OC192_B, 4 MHz to 80 MHz
SONET_OC192_C, 50 kHz to 80 MHz
Brick Wall,_800 Hz to 80 MHz
1000
19.44 MHz in, 161.1328125 MHz out
155.52 MHz in, 622.08 MHz out
Jitter Band
10000
Preliminary Rev. 0.2
Offset Frequency (Hz)
100000
1000000
Jitter, RMS
TBD fs
TBD fs
TBD fs
TBD fs
TBD fs
TBD fs
10000000
100000000
Si5315
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