si5315 Silicon Laboratories, si5315 Datasheet - Page 31

• Manufacturer Part Number: si5315
• Description: Synchronous Ethernet/telecom Jitter Attenuating Clock Multiplier
• Manufacturer: Silicon Laboratories

4.2. PLL Self-Calibration
An internal self-calibration (ICAL) is performed before operation to optimize loop parameters and jitter
performance. While the self-calibration is being performed, the DSPLL is being internally controlled by the self-
calibration state machine. The LOL alarm will be active during ICAL. The self-calibration time t
Table 3, “AC Characteristics”.
Any of the following events will trigger a self-calibration:
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In any of the above cases, an internal self-calibration will be initiated if a valid input clock exists (no input alarm)
and is selected as the active clock at that time. The external crystal or reference clock must also be present for the
self-calibration to begin. If valid clocks are not present, the self-calibration state machine will wait until they appear,
at which time the calibration will start.
After a successful self-calibration has been performed with a valid input clock, no subsequent self calibrations are
performed unless one of the above conditions are met. If the input clock is lost following self-calibration, the device
enters holdover mode. When the input clock returns, the device relocks to the input clock without performing a self-
calibration.
4.2.1. Input Clock Stability during Internal Self-Calibration
An exit from reset must occur when the selected CKINn clock is stable in frequency with a frequency value that is
within the device operating range. The other CKINs must also either be stable in frequency or squelched during a
reset.
4.2.2. Self-Calibration caused by Changes in Input Frequency
If the selected CKINn varies by 500 ppm or more in frequency since the last calibration, the device may initiate a
self-calibration.
4.2.3. Device Reset
Upon powerup, the device internally executes a power-on-reset (POR) which resets the internal device logic. The
pin RST can also be used to initiate a reset. The device stays in this state until a valid CKINn is present, when it
then performs a PLL Self-Calibration (See 4.2. "PLL Self-Calibration”).
Power-on-reset (POR)
Release of the external reset pin RST (transition of RST from 0 to 1)
Change in FRQSEL, FRQTBL, BWSEL, or XTAL/CLOCK pins
Internal DSPLL registers out-of-range, indicating the need to relock the DSPLL
Preliminary Rev. 0.2
LOCKHW
Si5315
is given in
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