74LVC74ABQ,115 NXP Semiconductors, 74LVC74ABQ,115 Datasheet - Page 7

• Manufacturer Part Number: 74LVC74ABQ,115
• Description: IC DUAL D FF POS-EDGE 14DHVQFN
• Manufacturer: NXP Semiconductors
• Series: 74LVCr
• Type: D-Typer

Specifications of 74LVC74ABQ,115

• Package / Case: 14-VQFN Exposed Pad, 14-HVQFN, 14-SQFN, 14-DHVQFN
• Function: Set(Preset) and Reset
• Output Type: Differential
• Number Of Elements: 2
• Number Of Bits Per Element: 1
• Frequency - Clock: 250MHz
• Trigger Type: Positive Edge
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 2
• Logic Family: LVC
• Logic Type: D-Type Edge Triggered Flip-Flop
• Polarity: Inverting/Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 2.5 ns at 3.3 V
• High Level Output Current: - 24 mA
• Supply Voltage (max): 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 1.2 V
• Delay Time - Propagation: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Delay Time - Propagation: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 74LVC74ABQ-G; 74LVC74ABQ-G; 935273502115

NXP Semiconductors
[4]
11. AC waveforms
74LVC74A_6
Product data sheet
Fig 7. The clock input (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up,
C
P
f
C
V
N = number of inputs switching
i
(C
D
CC
PD
= input frequency in MHz; f
L
= output load capacitance in pF
= C
L
is used to determine the dynamic power dissipation (P
= supply voltage in Volts
The shaded areas indicate when the input is permitted to change for predictable output performance.
V
V
V
the nCP to nD hold times, and the maximum frequency
PD
V
M
M
OL
CC
= 1.5 V at V
= 0.5
and V
2
V
CC
f
o
2
OH
) = sum of the outputs
V
CC
f
are typical output voltage levels that occur with the output load.
i
CC
at V
N + (C
2.7 V;
CC
nCP input
nQ output
nQ output
nD input
o
< 2.7 V;
= output frequency in MHz
L
V
CC
GND
GND
V
V
V
V
OH
OH
2
OL
OL
V
V
I
I
f
o
) where:
V
M
t
PLH
t
Rev. 06 — 4 June 2007
su
Dual D-type flip-flop with set and reset; positive-edge trigger
D
t
V
in W).
h
M
V
V
t
W
M
M
t
PHL
1/f
max
t
PHL
t
su
t
h
t
mna422
PLH
74LVC74A
© NXP B.V. 2007. All rights reserved.
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