sc26c198 NXP Semiconductors, sc26c198 Datasheet - Page 19

• Manufacturer Part Number: sc26c198
• Description: Octal Uart With Ttl Compatibility At 3.3v And 5v Supply Voltages
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 7. Data Clock Mux
CCLK maximum rate is 8MHz. Data clock rates will follow exactly the ratio of CCLK to 3.6864MHz.
Table 8. CR – Command Register
CR is used to write commands to the Octal UART.
CR[2] – Lock TxD and RxFIFO enables
If set, the transmitter and receiver enable bits, CR[1:0] are not
significant. The enabled/disabled state of a receiver or transmitter
can be changed only if this bit is at zero during the time of the write
to the command register. WRITES TO THE UPPER BITS OF THE
CR WOULD USUALLY HAVE CR[2] AT 1 to maintain the condition
of the receiver and transmitter. The bit provides a mechanism for
writing commands to a channel, via CR[7:3], without the necessity of
keeping track of or reading the current enable status of the receiver
and transmitter.
CR[1] – Enable Transmitter
A one written to this bit enables operation of the transmitter. The
TxRDY status bit will be asserted. When disabled by writing a zero
to this bit, the command terminates transmitter operation and resets
the TxRDY and TxEMT status bits. However, if a character is being
transmitted or if characters are loaded in the TxFIFO when the
transmitter is disabled, the transmission of the all character(s) is
completed before assuming the inactive state.
CR[0] – Enable Receiver
A one written to this bit enables operation of the receiver. If not in
the special wake up mode, this also forces the receiver into the
search for start bit state. If a zero is written, this command
terminates operation of the receiver immediately – a character being
received will be lost. The command has no effect on the receiver
status bits or any other control registers. If the special wake–up
mode is programmed, the receiver operates even if it is disabled
(see Wake–up Mode).
CR[7:3] – Miscellaneous Commands ( See Table below)
1995 May 1
Register Table”
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
Clock Select Code
“Command
Command
codes see
Bits 7:3
Channel
00000
00001
00010
00011
00100
00101
00110
01000
01001
01010
01011
01100
01101
00111
01110
01111
Lock TxD and
RxFIFO
enables
Bit 2
CCLK = 3.6864 MHz
Enable Tx
Clock selection,
BRG – 14.4K
Bit 1
BRG – 1200
BRG – 1800
BRG – 2400
BRG – 3600
BRG – 4800
BRG – 7200
BRG – 9600
BRG – 150
BRG – 200
BRG – 300
BRG – 450
BRG – 600
BRG – 900
BRG – 50
BRG – 75
Enable Rx
Bit 0
354
Clock Select Code
The encoded value of this field can be used to specify a single
command as follows:
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
10000
10001
10010
10100
10101
10011
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
No command.
Reserved
Reset receiver. Resets the receiver as if a hardware reset
had been applied. The receiver is disabled and the FIFO
pointer is reset to the first location effectively discarding all
unread characters in the FIFO.
Reset transmitter. Resets the transmitter as if a hardware
reset had been applied.
Reset error status. Clears the received break, parity error,
framing error, and overrun error bits in the status register
(SR[7:4]). Used in character mode to clear overrun error
status (although RB, PE and FE bits will also be cleared),
and in block mode to clear all error status after a block of
data has been received.
Reset break change interrupt. Causes the break detect
change bit in the interrupt status register (ISR[2]) to be
cleared to zero.
Start break. Forces the TxD output low (spacing). If the
transmitter is empty, the start of the break condition will be
delayed up to two bit times. If the transmitter is active, the
break begins when transmission of the current character
is completed. If there are characters in the TxFIFO, the
start of break is delayed until those characters, or any
others loaded after it have been transmitted (TxEMT must
be true before break begins). The transmitter must be
enabled to start a break.
Stop break. The TxD line will go high (marking) within two
bit times. TxD will remain high for one bit time before the
next character, if any, is transmitted.
Assert RTSN. Causes the RTSN output to be asserted
(low).
Negate RTSN. Causes the RTSN output to be negated
(high).
Note: The two commands above actually reset and
set, respectively, the I/O2 or I/O1 pin associated with
the I/OPIOR register.
Reserved
Reserved
Reserved
SC26C198 SC68C198
SC26L198 SC68L198
I/O2 rcvr, I/O3 xmit –16x
I/O2 rcvr, I/O3 xmit–1x
CCLK = 3.6864 MHz
Clock selection,
BRG – 115.2K
BRG – 230.4K
BRG – 19.2K
BRG – 28.2K
BRG – 38.4K
BRG – 57.6K
BRG C/T 0
BRG C/T 1
Reserved
Reserved
Reserved
Reserved
G
G
IN
IN
0
1
Product specification