sc26c198 NXP Semiconductors, sc26c198 Datasheet - Page 4

• Manufacturer Part Number: sc26c198
• Description: Octal Uart With Ttl Compatibility At 3.3v And 5v Supply Voltages
• Manufacturer: NXP Semiconductors

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
Philips Semiconductors
NOTE: Many output pins will have very fast edges, especially when lightly loaded (less than 20 pf.) These edges may move as fast as 1 to 3 ns
fall or rise time. The user must be aware of the possible generation of ringing and reflections on improperly terminated interconnections. See
previous note on Sclk noise under pin assignments.
ABSOLUTE MAXIMUM RATINGS
NOTES:
1995 May 1
Pin Description
SClk
CEN
A(7:0)
D(7:0)
W_RN
DACKN
IRQN
IACKN
TD(a–h)
RD(a–h)
I/O0(a–d)
I/O1(a–d)
I/O2(a–d)
I/O3(a–d)
G
G
RESETN
X1/CCLK
X2
Power Supplies
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
IN
OUT
the functional operation of the device at these or any other conditions above those indicated in the Operation Section of this specification is
not implied.
MNEMONIC
(1:0)
SYMBOL
0
T
PD5
PD3
V
V
T
STG
CC
SS
A
TYPE
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
Write Read not control: When high indicates that the host CPU will write to a 26C198 register or transmit FIFO.
Host system clock. Used to time operations in the Host Interface and clock internal logic. Must be greater
than twice the frequency of highest X1, Counter/Timer, TxC (1x) or RxC (1x) input frequency.
Chip select: Active low. When asserted, allows I/O access to OCTART registers by host CPU. W_RN signal
indicates direction. (Must not be active in IACKN cycle)
Address lines (A[6] is NOT used. See ”Host Interface” )
8–bit bi–directional data bus. Carries command and status information between 26C198 and the host CPU.
Used to convey parallel data for serial I/O between the host CPU and the 26C198
When low, indicates a read cycle. 0 = Read; 1 = Write
Data Acknowledge: Active low. When asserted, it signals that the last transfer of the D lines is complete.
Open drain.
Interrupt Request: Active low. When asserted, indicates that the 26C198 requires service for pending
interrupt(s). Open drain.
Interrupt Acknowledge: Active low. When asserted, indicates that the host CPU has initiated an interrupt
acknowledge cycle. (Do not use CEN in an IACKN cycle)
Transmit Data: Serial outputs from the 8 UARTs.
Receive Data: Serial inputs to the 8 UARTs
Input/Output 0: Multi–use input or output pin for the UART.
Input/Output 1: Multi–use input or output pin for the UART.
Input/Output 2: Multi–use input or output pin for the UART.
Input/Output 3: Multi–use input or output pin for the UART.
Global general purpose inputs, available to any/all channels.
Global general purpose outputs, available from any channel.
Master reset: Active Low. Must be asserted at power up and may be asserted at other times to reset and
restart the system. See “Reset Conditions” at end of register map. Minimum width 10 SCLK.
Crystal 1 or Communication Clock: This pin may be connected to one side of a 2–8 MHz crystal. It may
alternatively be driven by an external clock in this frequency range. Standard frequency = 3.6864 MHz
Crystal 2: If a crystal is used, this is the connection to the second terminal. If a clock signal drives X1, this pin
must be left unconnected.
16 pins total 8 pins for Vss, 8 pins for Vcc
Operating ambient temperature range
Power Dissipation at V
Power Dissipation at V
Voltage from any pin to GND
Storage temperature range
Voltage from V
PARAMETER
DD
CC
CC
to GND
= 5.0 Volts
= 3.3 Volts
339
DESCRIPTION
-0.5 to V
See Note 3
-65 to +150
-0.5 to +7.0
SC26C198 SC68C198
RATING
SC26L198 SC68L198
1.2
0.5
CC
+ 0.5
Product specification
UNIT
W
W
V
V
C
C