sc26c198 NXP Semiconductors, sc26c198 Datasheet - Page 39
![no-image](/images/manufacturer_photos/0/4/487/nxp_semiconductors_sml.jpg)
sc26c198
Manufacturer Part Number
sc26c198
Description
Octal Uart With Ttl Compatibility At 3.3v And 5v Supply Voltages
Manufacturer
NXP Semiconductors
Datasheet
1.SC26C198.pdf
(49 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
sc26c198C1A
Manufacturer:
NS
Quantity:
12 388
Part Number:
sc26c198C1A
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Philips Semiconductors
AC ELECTRICAL CHARACTERISTICS
1995 May 1
RESET TIMING
BUS TIMING
I/O PORT PIN TIMING
INTERRUPT TIMING
Tx / Rx CLOCK TIMING, External
TRANSMITTER TIMING
RECEIVER TIMING
Sclk TIMING
SYMBOL
SYMBOL
T/RFsclk
TsSTRT
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
Tsclkh
Tsclkl
Fsclk
t
t
t
RXH
t
t
t
t
t
RWS
RWH
RWD
t
t
t
t
t
RES
t
t
t
t
STP
t
t
t
t
t
t
t
f
t
f
t
TXD
TCS
RXS
t
AS
AH
CS
CS
CH
CH
DD
DF
DF
DS
DH
PS
PH
PD
DD
RX
RX
RF
TX
TX
IR
3
FIGURE
FIGURE
RESET pulse width
A0-A7 setup time before Sclk C3 rising edge
A0-A7 hold time after Sclk C3 rising edge
CEN setup time before Sclk C1 high (ASYNC)
CEN setup time before Sclk C2 high (SYNC)
CEN hold time after Sclk C3 high (SYNC)
CEN hold time after Sclk C4 high (ASYNC)
CEN high after C4 end. To terminate cycle (SYNC)
W-Rn setup time before Sclk C2 rising edge
W-Rn hold time after Sclk C3 rising edge
Read cycle Data valid after Sclk C3 falling edge
Read cycle data bus floating after CEN high (ASYNC)
Read cycle data bus floating after C4 end (SYNC)
Write cycle data setup time before Sclk C4 rising edge
Write cycle data hold time after Sclk C4 rising edge
High time between CEN low (ASYNC)
I/O input setup time before Sclk C3 falling edge (Read IPR)
I/O input hold time after Sclk C4 rising edge (Read IPR)
I/O output valid from:
IRQN from:
Interrupt vector valid after C3 falling edge, IACKN cycle
RxC high or low time
RxC frequency (16 X)
TxC high or low time
TxC frequency (16 X)
Tx / Rx clock rise and fall times
TxD output delay from TxC low
TxC output delay from TxD output data
RxD data setup time to RxC high (data)
RxD data hold time from RxC high (data)
RxD data setup time to RxC high (Start Bit)
Min low time at Vil (0.8V)
Min high time at Vih (2.0V)
Sclk frequency
Sclk rise/fall time (0.8 to 2.0Volts)
Write Sclk C4 rising edge (write to I/OPIOR)
Internal interrupt source active bid
Software reset to IRQN inactive
Write IMR (clear IMR bit after C4 end)
2
(1 X)
(1 X)
5
PARAMETER
PARAMETER
(26C198 and 68C198)
1
374
17 / 32
MIN
-20
10
10
18
15
25
20
25
30
12
20
18
22
20
20
30
30
11
11
5
5
5
0
0
0
0
SC26C198 SC68C198
SC26L198 SC68L198
1.5 Sclk
1.5 Sclk
1.5 Sclk
LIMITS
TYP
12
25
20
20
15
18
10
25
3
3
MAX
3 / 3
100
18
37
35
35
50
43
50
37
16
16
20
20
33
1
1
Product specification
16X clk
UNIT
UNIT
MHz
MHz
MHz
Sclk
Sclk
Sclk
Sclk
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns