cs4227 Cirrus Logic, Inc., cs4227 Datasheet - Page 18

• Manufacturer Part Number: cs4227
• Description: Six Channel, 20-bit Codec
• Manufacturer: Cirrus Logic, Inc.

2.6.2
In I
Data is clocked into and out of the part by the clock,
SCL, with the clock to data relationship as shown
in Figure 12. There is no CS pin. Pins AD0, AD1
form the partial chip address. The upper 5 bits of
the 7 bit address field must be 00100. To commu-
nicate with a CS4227, the LSBs of the chip address
field, which is the first byte sent to the CS4227,
should match the settings of the AD1, AD0 pins.
The eighth bit of the address bit is the R/W bit (high
for a read, low for a write). If the operation is a
write, the next byte is the Memory Address Pointer
which selects the register to be read or written. If
the operation is a read, the contents of the register
pointed to by the Memory Address Pointer will be
output. Setting the auto increment bit in MAP, al-
lows successive reads or writes of consecutive reg-
isters. Each byte is separated by an acknowledge
bit. Use of the I
quires a license from Philips. I
tered trademark of Philips Semiconductors.
2.6.3
All registers can be written and read back, except
the DAC Status Report Byte (#10) and ADC Status
Report Byte (#13), which are read only. See the fol-
lowing bit definition tables for bit assignment in-
formation.
18
2
C
®
mode, SDA is a bidirectional data line.
I
Control Port Bit Definitions
2
C
®
Mode
2
C bus
SDA
SCL
Note 1: If operation is a write, this byte contains the Memory Address Pointer, MAP.
®
Start
compatible interface re-
00100
2
C bus
Figure 12. Control Port Timing, I
ADDR
AD1-0
®
is a regis-
R/W
ACK
2.7
Upon power up, the user should hold PDN = 0 for
approximately 1ms. In this state, the control port is
reset to its default settings. At the end of the PDN,
the device remains in a low power mode in which
CMOUT will not supply current, but the control
port is active. The desired settings should be loaded
while keeping the RS bit set to 1. Normal operation
is achieved by setting the CE bit to zero in the
Clock Mode Byte (#1) and the RS bit to zero in the
Converter Control Byte (#2). Once done, the part
powers up and an offset calibration occurs. This
process lasts approximately 50 ms.
Reset/power down is achieved by lowering the
PDN pin causing the part to enter power down.
Once PDN goes high, the control port is functional
and the desired settings should be loaded in while
keeping the RS bit set to 1. The remainder of the
chip remains in a low power reset state until the RS
bit in the Convertor Control Byte is set to 0. After
clearing the RS bit, the CE bit (Clock Enable) in the
Clock Mode Byte (#1) should also be set to zero.
The CS4227 will also enter a stand by mode if the
master clock source stops for approximately 10 µs
or if the LRCK is not synchronous to the master
clock. The control port will retain its current set-
tings.
DATA
1-8
Note 1
Power-up/Reset/Power Down Mode
2
ACK
C
®
Mode
DATA
1-8
ACK
Stop
CS4227
DS281PP2