cs4227 Cirrus Logic, Inc., cs4227 Datasheet - Page 19

• Manufacturer Part Number: cs4227
• Description: Six Channel, 20-bit Codec
• Manufacturer: Cirrus Logic, Inc.

2.8
Output offset voltage is minimized by an internal
calibration cycle. A calibration will automatically
occur anytime the part comes out of reset, includ-
ing the power-up reset, or when the master clock
source to the part changes by changing the CE or CI
bits in the Clock Mode Byte.
The CS4227 can be re-calibrated whenever de-
sired. A control bit, CAL, in the Converter Control
Byte, is provided to initiate a calibration. The se-
quence is:
1) Set CAL to 1, the CS4227 sets CALP to 1 and
2) CALP will go to 0 when the calibration is com-
Additional calibrations can be implemented by set-
ting CAL to 0 and then to 1.
2.9
The CS4227 is capable of digital de-emphasis for
32, 44.1, or 48 kHz sample rates. Implementation
of digital de-emphasis requires reconfiguration of
the digital filter to maintain the filter response
shown in Figure 13 at multiple sample rates. The
Auxiliary Port Control Byte selects the de-empha-
sis control method. De-emphasis may be enabled
under hardware control, using the DEM pin
(DEM2/1/0=4,5,6), or by software control using
the DEM bit (DEM2/1/0=0,1,2,3)
2.10 Hold Function
If the digital audio source presents invalid data to
the CS4227, the CS4227 may be configured to
cause the last valid digital input level to be held
constant (this sounds much better than a potentially
random output level). Holding the previous output
sample occurs when the user asserts the HOLD pin
(HOLD = 1) at any time during the stereo sample
period. During a HOLD condition, AUXPort input
data is ignored. DAC outputs can be automatically
muted after an extended HOLD period (>15 sam-
DS281PP2
begins to calibrate.
pleted.
DAC Calibration
De-Emphasis
ples) by setting the MOH bit = 0 in the Auxiliary
Port Control Byte. DACs will not be automatically
muted when MOH = 1. When the HOLD pin is de-
asserted (HOLD = 0), the DAC outputs will return
to one of two different states controlled by the
UMV (Unmute on Valid Data) bit in the Auxiliary
Port Control Byte. When UMV = 0, the DAC out-
puts will unmute when the HOLD is removed.
When UMV = 1, the DACs must be unmuted in the
DAC Control Byte after the HOLD is removed.
This allows the user to unmute the DAC after the
invalid data has passed through the DSP.
2.11 Power Supply, Layout, and
The CS4227, along with associated analog circuit-
ry, should be positioned near the split between
ground planes, and have its own, separate, ground
plane (see Figure 14). Preferably, it should also
have its own power plane. The +5 V supply must be
connected to the CS4227 via a ferrite bead, posi-
tioned closer than 1" to the device. A single con-
nection between the CS4227 ground and the board
ground should be positioned as shown in Figure 14.
The location of the 1 µF CMOUT filtering capica-
tor should be as close to the CS4227 as possible.
See Crystal's layout Applications Note, and the
CDB4227 evaluation board data sheet for recom-
mended layout of the decoupling components.
-10dB
Gain
dB
0dB
Grounding
Figure 13. De-emphasis Curve.
T1=50 s
F1
F2
CS4227
T2 = 15 s
Frequency
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