ad5504 Analog Devices, Inc., ad5504 Datasheet - Page 11

• Manufacturer Part Number: ad5504
• Description: High Voltage, Quad Channel 12-bit Voltage Output Dac
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
THEORY OF OPERATION
The AD5504 contains 4 DACs, 4 output amplifiers and a
precision reference in a single package. The architecture of a
single DAC channel consists of a 12-bit resistor-string DAC
followed by an output buffer amplifier. The part operates from a
single supply voltage of 10 V to 62 V. The DAC output voltage
range is selected via the range-select, R_SEL , pin. The DAC
output range is 0 V to 30 V if R_SEL is held high and 0 V to
60 V if R_SEL is held low. Data is written to the AD5504 in a
16-bit word format (see Table 7), via a serial interface.
POWER-UP STATE
On power-up, the Power-on-Reset circuitry clears the bits of the
Control register (see Table 9) to 0. This ensures that the analog
section is initially powered down, which helps reduce power
consumption, and that the thermal shutdown mode is enabled
but not activated. This allows the user to program the DAC
registers to the required values while typically consuming only
TBD
ensures that all the input and DAC registers power up in a
known condition, 0x000, and remain there until a valid write to
the device has taken place. The analog section can be powered
up by setting any or all of bits C2 to C5 of the Control register
to 1.
POWER-DOWN MODE
Each DAC channel can be individually powered up or powered
down in groups by programming the Control register (see Table
9). When the DAC channel is powered down the associated
analog circuitry is turn off to reduce power consumption. The
digital section of the AD5504 remains powered up. The output
of the DAC amplifier can be three-stated or connected to
AGND via an internal 20KΩ resistor depending on the state of
bit C6 in the Control register. The power-down mode does not
change the contents of the DAC register. This ensures that the
DAC channel returns to its previous voltage when the power-
down bit is set to 1. The AD5504 also offers the user the
flexibility of updating the DAC registers during power-down.
The Control register can be read back at any time to check the
status of the bits.
DAC CHANNEL ARCHITECTURE
The architecture of a single DAC channel consists of a 12-bit
resistor-string DAC followed by an output buffer amplifier (see
Figure 7). The resistor-string section is simply a string of
resistors, each of value R, from V
reference, to AGND. This type of architecture guarantees DAC
monotonicity. The 12-bit binary digital code loaded to the DAC
register determines at which node on the string the voltage is
tapped off before being fed into the output amplifier. The data
format for the AD5504 is straight binary as shown in Table 6.
The output amplifier multiplies the DAC output voltage to give
a fixed linear voltage output range of 0 V to 60 V if R_SEL =0 or
0 V to 30 V if R_SEL =1. Each output amplifier is capable of
driving a 40K
μ
A of supply current. The power-on-reset circuitry also
Ω
load while allowing an output swing within the
REF
, generated by the precision
Rev. Pr B | Page 11 of 15
range of AGND +TBD V and V
As the DAC architecture gives a fixed voltage output range of 0
to 30 V or 0 to 60 V the user should set V
60.5 V to use the maximum DAC resolution.
Table 6. DAC Data Format
DAC Value
0b0000 0000 0000
0b0000 0000 0001
0b0000 0000 0010
0b0111 1111 1111
0b1000 0000 0000
0b1111 1111 1110
0b1111 1111 1111
SELECTING THE OUTPUT RANGE
The output range of the DACs is selected by the R_SEL pin.
When the R_SEL pin is connected to logic 1 the DAC output
voltages can be set between 0 V and 30 V. When the R_SEL pin
is connected to logic 0 the DAC output voltages can be set
between 0 V and 60 V. The state of R_SEL can be changed any
time when the serial interface is not being used, i.e. not during a
read or write operation. When the R_SEL pin is changed, the
voltage on the output pin remains the same until the next write
to the DAC register (and LDAC is brought low). For example, if
the user writes 0x800 to the DAC register when in 30 V mode
( R_SEL =1) the output voltage is 15 V (assuming LDAC is low
or has been pulsed low). When the user switches to 60 V mode
( R_SEL =0) the output stays at 15 V until the user writes a new
value to the DAC register. LDAC must be low or be pulsed low
for the output to change.
CLR FUNCTION
The AD5504 has a hardware CLR pin that is an asynchronous
clear input. The CLR input is falling edge sensitive. Bringing the
CLR line low clears the contents of the Input register and the
DAC registers to 0x000. The CLR pulse activation time, i.e. the
falling edge of CLR to when the output starts to change, is typically
TBD ns.
REGISTER
INPUT
Figure 11. DAC Channel Architecture (Single Channel Shown)
12
REGISTER
DAC
30 V Mode
0.000000000
0.007324219
0.014648438
14.99267578
15.00000000
29.98535156
29.99267578
12
REFERENCE
PRECISION
DD
AGND
– TBD V.
DAC
Output Voltage
DD
to at least 30.5 V or
GAIN
60 V Mode
0.000000000
0.014648438
0.029296875
29.98535156
30.00000000
59.97070313
59.98535156
AD5504
V
OUTX