ad5504 Analog Devices, Inc., ad5504 Datasheet - Page 14

• Manufacturer Part Number: ad5504
• Description: High Voltage, Quad Channel 12-bit Voltage Output Dac
• Manufacturer: Analog Devices, Inc.

AD5504
Table 9. Control Register Functions
DB15
R/ W
C2 = 1 : DAC channel A power-up
INTERFACING EXAMPLES
The SPI interface of the AD5504 is designed to allow the it to be
easily connected to industry-standard DSPs and microcontrollers.
Figure 12 shows how the AD5504 can be connected to the
Analog Devices, Inc., Blackfin® DSP. The Blackfin has an integrated
SPI port that can be connected directly to the SPI pins of the
AD5504, as well as programmable input/output pins that can be
used to set or read the state of the digital input or output pins
associated with the interface.
Read only bit. This bit should be 0 when writing to the Control register
C0 = 0 : device is not in thermal shutdown mode
C0 = 1 : device is in thermal shutdown mode
C1 = 0 : enable thermal shutdown mode(Default)
C1 =1 : disable thermal shutdown mode
C2 = 0 : DAC channel A power-down (Default)
C3 = 0 : DAC channel B power-down (Default)
C3 = 1 : DAC channel B power-up
C4 = 0 : DAC channel C power-down (Default)
C4 = 1 : DAC channel C power-up
C5 = 0 : DAC channel D power-down (Default)
C5 = 1 : DAC channel D power-up
C6 = 0 : Ouputs connected to AGND through a 20KΩ resistor (Default)
C6 = 1 : Outputs are three-stated
(If bits C2 to C5 are set to 0 then the part is placed in power-down mode)
ADSP-BF531
DB14
1
Figure 12. Interfacing to a Blackfin DSP
DB13
1
SPISELx
MOSI
MISO
PF10
SCK
PF9
PF8
PF7
DB12
1
DB11
X
DB10
X
SYNC
SCLK
SDI
SDO
R_SEL
LDAC
CLR
ALARM
AD5504
DB9
X
Rev. Pr B | Page 14 of 15
DB8
X
DB7
X
The Analog Devices
two serial ports (SPORTs). Figure 13 shows how one SPORT
can be used to control the AD5504. In this example, the transmit
frame synchronization (TFS) pin is connected to the receive
frame synchronization (RFS) pin. The transmit and receive
clocks (TCLK and RCLK) are also connected together. The user
can write to the AD5504 by writing to the transmit register. If a
read operation is being performed the data is clocked out of the
AD5504 on the last 12 SCLKs. The DSP receive interrupt can be
used to indicate when the read operation is complete.
ADSP-21065L
DB6
C6
Figure 13. Interfacing to an ADSP-21065L DSP
DB5
C5
RCLKx
TCLKx
FLAG
FLAG
FLAG
FLAG
DRxA
RFSx
DTxA
TFSx
Preliminary Technical Data
ADSP-21065L
0
1
2
3
DB4
C4
DB3
C3
is a floating point DSP with
DB2
C2
SYNC
SCLK
SDI
SDO
R_SEL
LDAC
CLR
ALARM
AD5504
DB1
C1
DB0
C0