ad5504 Analog Devices, Inc., ad5504 Datasheet - Page 8

• Manufacturer Part Number: ad5504
• Description: High Voltage, Quad Channel 12-bit Voltage Output Dac
• Manufacturer: Analog Devices, Inc.

AD5504
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
CLR
SYNC
SCLK
SDI
SDO
DGND
AGND
LDAC
V
V
V
V
R_SEL
V
ALARM
V
OUTD
OUTC
OUTB
OUTA
DD
LOGIC
Description
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored.
When CLR is activated, the Input register and the DAC register are set to 0x000 and the outputs to zeroscale.
Falling Edge Synchronisation Signal.
This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift
register and data is transferred in on the falling edges of the following clocks. The selected DAC register is
updated following the 16th clock cycle unless SYNC is taken high before this edge, in which case the rising
edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates up to 30 MHz.
Serial Data Input. This part has a 16-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
Serial Data Output. CMOS output. Serves as readback function for all DAC and Contol registers. Data is clocked
out on the rising edge of SCLK and is valid on the falling edge of SCLK
Digital Ground Pin.
Analog Ground Pin.
Load DAC Input. Pulsing this pin low allows any or all DAC registers to be updated if the Input registers have
new data. This allows all DAC outputs to update simultaneously. Alternatively, this pin can be tied permanently
low.
Buffered Analog Output Voltage from DAC D
Buffered Analog Output Voltage from DAC C
Buffered Analog Output Voltage from DAC B
Buffered Analog Output Voltage from DAC A
Range Select Pin. Tying this pin to DGND selects a DAC output range of 0 V to 60 V, alternatively tying R_SEL to
VLOGIC select a DAC output range of 0V to 30V.
Positive Analog Power Supply; 10 V to 62 V for the specified performance. This pin should be decoupled with
0.1μF ceramic capacitors and 10 μF capacitors.
Active Low CMOS Output Pin. This pin flags an alarm if the temperature on the die exceeds 130ºC.
Logic Power Supply; 2.3 V to 5.5 V. This pin should be decoupled with 0.1μF ceramic capacitors and 10 μF
capacitors.
DGND
AGND
SYNC
LDAC
SCLK
SDO
CLR
SDI
1
2
3
4
5
6
7
8
Figure 5. TSSOP Configuration
(Not to Scale)
Rev. Pr B | Page 8 of 15
AD5504
TOP VIEW
15
14
13
12
11
10
16
9
V
ALARM
V
R_SEL
V
V
V
V
LOGIC
DD
OUTA
OUTB
OUTC
OUTD
Preliminary Technical Data