ad5504 Analog Devices, Inc., ad5504 Datasheet - Page 5

• Manufacturer Part Number: ad5504
• Description: High Voltage, Quad Channel 12-bit Voltage Output Dac
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
TIMING CHARACTERISTICS
V
Table 3.
Parameter
1
2
3
4
5
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
Maximum SCLK frequency is 30 MHz.
Under load conditions outlined in Figure 2
Time from V
Time required from execution of power-on software command to when the DAC outputs have settled.
DD
= 30 V, V
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
17
18
20
21
DD
1
10
11
12
13
14
15
16
19
2
3
4
5
6
7
8
9
2
3
3
4
5
/V
LOGIC
LOGIC
supplies powered-up to when a digital interface command can be executed.
= 2.3 V to 5.5 V and −40°C < T
Limit
TBD(200)
TBD(20)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
1
7.5
33
10
10
10
20
45
50
5
0
9
9
TO OUTPUT
Unit
PIN
ns max
us max
us max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns typ
Figure 2. Load Circuit for SDO Timing Diagram
A
50pF
< +105°C. All specifications T
C
L
DD
200µA
200µA
) and timed from a voltage level of (V
Rev. Pr B | Page 5 of 15
Test Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK falling edge ignore
SCLK falling edge to SYNC fall ignore
LDAC pulse width low
SCLK falling edge to LDAC rising edge
CLR pulse width low
SCLK falling edge to LDAC falling edge
CLR pulse activation time
ALARM clear time
SCLK rising edge to SDO valid
SCLK to SDO Data hold time
SYNC rising edge to SCLK rising edge ignore
Power-On-Reset time. (not shown)
Power-on time. (not shown)
I
I
OL
OH
V
OH
(MIN) – V
MIN
to T
2
IL
OL
+ V
MAX
(MAX)
IH
, unless otherwise noted.
)/2.
AD5504