mg84fl54b Megawin Technology, mg84fl54b Datasheet - Page 38

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mg84fl54b

Manufacturer Part Number
mg84fl54b
Description
Full-speed Usb Micro-controller
Manufacturer
Megawin Technology
Datasheet
12.2. Interrupt System
12.3. Note on Interrupt during ISP/IAP
During ISP/IAP, the CPU halts for a while for internal ISP/IAP processing. At this time, the interrupt will queue
up for being serviced if the interrupt is enabled previously. Once the ISP/IAP is complete, the CPU continues
running and the interrupts in the queue will be serviced immediately if the interrupt flag is still active. Users,
however, should be aware of the following:
(1) Any interrupt can not be serviced in time during the CPU halts for ISP/IAP processing.
(2) The low-level triggered external interrupts, /INT0, /INT1, INT2 and INT3, should keep active until the
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ISP/IAP is complete, or they will be neglected.
KBIF
SPIF
USB
/INT0
/INT1
INT2
INT3
TF0
TF1
TF2
SI
RI
TI
Individual Enable
IE0
IE1
IE Register
MG84FL54B Data Sheet
Global Enable
IP Register
High Priority Level Interrupt
Low Priority Level Interrupt
Interrupt Polling
Sequence
MEGAWIN

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