mg84fl54b Megawin Technology, mg84fl54b Datasheet - Page 76
![no-image](/images/no-image-200.jpg)
mg84fl54b
Manufacturer Part Number
mg84fl54b
Description
Full-speed Usb Micro-controller
Manufacturer
Megawin Technology
Datasheet
1.MG84FL54B.pdf
(94 pages)
- Current page: 76 of 94
- Download datasheet (2Mb)
20. In-System-Programming (ISP)
The Flash program memory supports both parallel programming and serial In-System Programming (ISP).
Parallel programming mode offers high-speed programming. ISP allows a device to be reprogrammed in the
end product under software control. The capability to field update the application firmware makes a wide range
of applications possible.
Prior to using the ISP feature, the user should configure an ISP-memory by a universal Writer or Programmer.
Refer to Section “Hardware Option” for the ISP-memory configuration.
The following special function registers are related to ISP:
ISPCR: Address=E7H, ISP Control Register
IFADRH: Address=E3H, ISP Flash Address High Register
IFADRL: Address=E4H, ISP Flash Address Low Register
IFD: Address=E2H, ISP Flash Data Register
SCMD: Address=E6H, ISP Sequential Command Register.
ISPCR (Address=E7H, ISP Control Register)
Note: The reset value is #00000000B.
ISPEN: Set to enable ISP function.
SWBS:
SWRST: Write ‘1’ to trigger software reset.
MS2~MS0: ISP mode select, as listed below.
76
Software boot select. Set to select booting from ISP-memory, and clear to select booting from AP-memory
after software reset.
ISPEN
MS1
7
0
0
1
1
MS0
0
1
0
1
SWBS
6
SWRST
Byte Program
5
Page Erase
ISP Mode
Standby
Read
MG84FL54B Data Sheet
4
-
3
-
2
-
MS1
1
MS0
0
MEGAWIN
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