mg84fl54b Megawin Technology, mg84fl54b Datasheet - Page 75

• Manufacturer Part Number: mg84fl54b
• Description: Full-speed Usb Micro-controller
• Manufacturer: Megawin Technology

Bit6~4: Reserved.
Bit3: TXFFRC-- Transmit FIFO Write Complete.
Bit2~0: Reserved.
TXCNT (Transmit FIFO Byte Count Register, Endpoint-Indexed, Address=F6H, SYS/USB_reset=xxxx-xxxx,
Write-only)
Bit6~0: TXBC[6:0]-- Transmit Byte Count.
SIOCTL (Serial I/O Control Register, Address=C2H, SYS_RESET=xxxx-xxxx, Read-only)
Bit7: DPI-- USB DP port state, read only.
Bit6: DMI-- USB DM port state, read only.
Bit5~0: Reserved.
MEGAWIN
DPI
7
7
Set this bit to flush the entire transmit FIFO. All FIFO statuses are reverted to their reset states. Hardware
clears this bit when the flush operation is completed.
Set this bit to release the transmit FIFO when data set write is complete. Hardware clears this bit after the
FIFO release operation has been finished. Firmware should write this bit only after firmware finished
writing TXCNT register.
Stored the byte count for the data packet in the transmit FIFO specified by EPINDEX.
Read the port status on USB DP.
Read the port status on USB DM.
-
TXBC6
DMI
6
6
TXBC5
5
5
-
TXBC4
4
4
-
MG84FL54B Data sheet
TXBC3
3
3
-
TXBC2
2
2
-
TXBC1
1
1
-
TXBC0
0
0
-
75