s29cd-j Meet Spansion Inc., s29cd-j Datasheet
s29cd-j
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s29cd-j Summary of contents
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... Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Publication Number S29CD-J_CL-J_00 ™ Notice On Data Sheet Designations Revision B Amendment 2 S29CD-J & S29CL-J Flash Family Cover Sheet for definitions. Issue Date March 7, 2007 ...
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... Questions regarding these document designations may be directed to your local sales office range. Changes may also include those needed to clarify a IO S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B2 March 7, 2007 ...
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... Data Sheet (Preliminary) General Description The Spansion S29CD-J and S29CL-J devices are Floating Gate products fabricated in 110-nm process technology. These burst-mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks, using separate data and address pins. These products can operate MHz (32 Mb MHz (16 Mb), and use a single V 3 3.6 V (S29CL-J) that make them ideal for today’ ...
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... Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.2 Automatic Sleep Mode 12.3 Hardware RESET# Input Operation 12.4 Output Disable (OE#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 13. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 14. Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 IO S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B2 March 7, 2007 ...
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... Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 18.9 PQFP and Fortified BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 19. Appendix 19.1 Common Flash Memory Interface (CFI 20. Appendix 20.1 Command Definitions 21. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 March 7, 2007 S29CD-J_CL-J_00_B2 Power-up S29CD-J & S29CL-J Flash Family 5 ...
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... Figure 18.14 Synchronous Data Polling Timing/Toggle Bit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Figure 18.15 Sector Protect/Unprotect Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Figure 18.16 Alternate CE# Controlled Write Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 CC1 Power-up Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 IO S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B2 March 7, 2007 ...
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... Valid Configuration Register Bit Definition for IND/WAIT .26 Table 8.4 Burst Initial Access Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Table 8.5 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 8.6 Configuration Register After Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 8.7 S29CD-J & S29CL-J Flash Family Autoselect Codes (High Voltage Method .29 Table 8.8 DQ6 and DQ2 Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Table 8.9 Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Table 8.10 Reset Command Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Table 9.1 Sector Protection Schemes ...
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... S29CD-J/S29CL-J Valid Combinations QAI, QFI, QAM, QFM FAI, FFI, FAM, FFM 1M QAI, QFI, QAN, QFN FAI, FFI, FAN, FFN S29CD-J & S29CL-J Flash Family S29CD016J only S29CL016J only S29CD032J only S29CL032J only 00, 01, 02, 03, 10, 11, 12, 13 02, 03, 12, 13 ...
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... Input March 7, 2007 S29CD-J_CL-J_00_B2 Address lines for S29CD-J and S29CL-J (A18-A0 for 16Mb and A19-A0 for 32Mb). A9 supports 12V autoselect input. I/O Data input/output Chip Enable. This signal is asynchronous relative to CLK for the burst mode. ...
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... Erase Voltage Generator PGM Voltage Generator Chip Enable Output Enable Timer Burst Address IND/ Counter A –A0 max S29CD-J & S29CL-J Flash Family DQ DQ0 – max A –A0 max Input/Output V IO Buffers Data Latch Logic Y-Decoder ...
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... WE# COMMAND CE# REGISTER ADV# DQ –DQ0 max A –A0 max March 7, 2007 S29CD-J_CL-J_00_B2 Upper Bank Address Upper Bank X-Decoder Status Control X-Decoder Lower Bank Lower Bank Address S29CD-J & S29CL-J Flash Family OE# DQ –DQ0 max 11 ...
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... PQFP S29CD-J & S29CL-J Flash Family 64 DQ15 63 DQ14 62 DQ13 61 DQ12 CCQ DQ11 58 57 DQ10 56 DQ9 55 DQ8 54 DQ7 53 DQ6 ...
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... FOR DEVICES WITH LEAD PITCH OF 0. 0.076 mm FOR DEVICES WITH LEAD PITCH OF 0.50 mm. COPLANARITY IS MEASURED PER SPECIFICATION 06-500. 9. HALF SPAN (CENTER OF PACKAGE TO LEAD TIP) SHALL BE WITHIN ±0.0085". S29CD-J & S29CL-J Flash Family 0.20 MIN. FLAT SHOULDER 7˚ TYP. A 7˚ ...
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... DQ5 DQ9 A19 DQ2 DQ6 DQ10 DQ0 DQ4 DQ7 DQ8 DQ3 CCQ SS CCQ S29CD-J & S29CL-J Flash Family DQ20 DQ16 DQ18 IND/WAIT DQ19 OE# WE DQ17 CE ...
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... BALL COUNT WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW , e/2 BALL DIAMETER 8. N/A BALL PITCH - D DIRECTION 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALL PITCH - E DIRECTION BALLS. SOLDER BALL PLACEMENT S29CD-J & S29CL-J Flash Family ...
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... Contacting Spansion Obtain the latest list of company locations and contact information on our web site at www.spansion.com/about/location.html obtain the following related documents: S29CD-J & S29CL-J Flash Family http:// S29CD-J_CL-J_00_B2 March 7, 2007 ...
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... Product Overview The S29CD-J and S29CL-J families consist and 16 Mb, 2.6 volt-only (CD-J) or 3.3 volt-only (CL-J), simultaneous read/write, dual boot burst mode Flash devices optimized for today's automotive designs. These devices are organized in 1,048,576 double words (32 Mb) or 524,288 double words (16 Mb) and are capable of linear burst read ( double words) with or without wraparound ...
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... SG16 SA39 SG17 SA40 SG18 SA41 SG19 SA42 SG20 SA43 SG21 SA44 SG22 (Note 3) SA45 SG23 (Note 3) S29CD-J & S29CL-J Flash Family x32 Address Range Sector Size (A18:A0) (KDwords) 20000h–23FFFh 16 24000h–27FFFh 16 28000h–2BFFFh 16 2C000h–2FFFFh 16 30000h–33FFFh 16 34000h–37FFFh 16 38000h– ...
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... SA43 16 SA44 SA45 16 (Note S29CD-J & S29CL-J Flash Family x32 Sector Address Range Sector Size Group (A18:A0) (KDwords) 60000h–63FFFh 16 64000h–67FFFh 16 SG14 68000h–6BFFFh 16 6C000h–6FFFFh 16 70000h–73FFFh 16 SG15 74000h–77FFFh 16 78000h–7BFFFh ...
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... SA72 SG26 16 SA73 SG27 16 SA74 SG28 16 SA75 SG29 16 SA76 (Note 3) SG30 16 SA77 (Note 3) SG31 16 S29CD-J & S29CL-J Flash Family x32 Address Range Sector Size (A19:A0) (KDwords) (Note 2) 80000h–83FFFh 16 84000h–87FFFh 16 88000h–8BFFFh 16 8C000h–8FFFFh 16 90000h–93FFFh 16 94000h–97FFFh 16 98000h–9BFFFh 16 9C000h– ...
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... SA68 16 SA69 16 SA70 16 SA71 16 SA72 16 SA73 16 SA74 16 SA75 16 SA76 SA77 (Note 1) S29CD-J & S29CL-J Flash Family Sector x32 Address Range Sector Size Group (A19:A0) (KDwords) Bank 0 continued (Note 2) 80000h–83FFFh 16 84000h–87FFFh 16 SG16 88000h–8BFFFh 16 8C000h–8FFFFh 16 90000h–93FFFh 16 94000h–97FFFh ...
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... S29CD-J & S29CL-J Flash Family describes the required state of each Data Addresses (DQ0–DQ31 OUT HIGH Z HIGH Z HIGH Z X HIGH Z 00000001h, (protected) Sector Address, ...
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... Figure 8.1 Asynchronous Read Operation Address 1 Address 2 Address for another timing diagram. I S29CD-J & S29CL-J Flash Family to read data). OE# is the IL -t and CE# has been asserted for at ACC for timing specifications and to Figure 18.2, ...
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... Asynchronous Read Mode Only Set Burst Mode Configuration Register Configuration Register Command for Synchronous Mode Asynchronous Mode (D15 = 0) Synchronous Read Mode Only S29CD-J & S29CL-J Flash Family Section 8.4.1, 2-, 4-, 8- Section 8.4.3, Set Burst Mode Command for (D15 = 1)? is lengthened. IACC S29CD-J_CL-J_00_B2 March 7, 2007 ...
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... IND/ WAIT# signal is driven lists the valid combinations of the Configuration Register bits that impact the Figure 8.3 for the IND/WAIT# timing diagram. S29CD-J & S29CL-J Flash Family ) during the last transfer of data IL Output Data Sequence (Initial Access Address, x16) 0-1 ( ...
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... CR13-CR10. See Table 8.4 Burst Initial Access Delay CR11 CR10 S29CD-J & S29CL-J Flash Family Definition Initial Burst Access (CLK cycles S29CD-J_CL-J_00_B2 March 7, 2007 D0 ...
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... CLK 3rd CLK 4th CLK Three CLK Delay D0 D1 Four CLK Delay D0 Five CLK Delay Table 8.6 for the default Configuration Register settings.) The host system for sequence details. S29CD-J & S29CL-J Flash Family 5th CLK Section 20.1, Command ...
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... CR12 CR11 IAD3 IAD2 IAD1 CR5 CR4 CR3 Reserve Reserve Reserve Table 8.7. In addition, when verifying sector protection, the sector S29CD-J & S29CL-J Flash Family CR10 CR9 CR8 IAD0 DOC Reserve CR2 CR1 CR0 BL2 BL1 BL0 S29CD-J_CL-J_00_B2 March 7, 2007 ...
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... The system must write the reset command to exit the autoselect mode and return to reading the array data. See Table 8.7 for command sequence details. Table 8.7 S29CD-J & S29CL-J Flash Family Autoselect Codes (High Voltage Method) Description Manufacturer ID: Spansion Read Cycle 1 Read Cycle 2 ...
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... Figure 8.5 Program Operation START Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Increment Address Last Address? Programming Completed for program command sequence. S29CD-J & S29CL-J Flash Family No Yes Yes S29CD-J_CL-J_00_B2 March 7, 2007 ...
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... Section 8.8, Write Operation Status on page 34 illustrates the algorithm for the erase operation. Refer to for parameters and timing diagrams. Section 20.1, Command Definitions on page S29CD-J & S29CL-J Flash Family Table 20.1, Memory Array 32.) The device 39.) The time-out begins from the rising for information on these status Section 8 ...
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... Figure 8.6 Erase Operation START Write Erase Command Sequence Data Poll from System Embedded Erase algorithm in progress No Data = FFh? Yes Erasure Completed for erase command sequence. for more information. S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B2 March 7, 2007 ...
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... Section 8.8, Write Operation Status on page 34 for operations other than accelerated programming and accelerated chip HH shows the requirements for the unlock bypass command S29CD-J & S29CL-J Flash Family for more information. HH from the ACC input, upon HH ...
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... DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B2 March 7, 2007 ...
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... Figure 8.7, Data# Polling Algorithm, on page 35 Figure 8.7 Data# Polling Algorithm START Read DQ7–DQ0 Addr = VA Yes DQ7 = Data DQ5 = 1? Yes Read DQ7–DQ0 Addr = VA Yes DQ7 = Data? No FAIL S29CD-J & S29CL-J Flash Family shows the outputs for shows the Data# Polling timing PASS 35 ...
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... Thus, both status bits are required for sector and mode information. Refer to 8.8 to compare outputs for DQ2 and DQ6. See information Section 8.8.2, DQ6: Toggle Bit I on page 36 S29CD-J & S29CL-J Flash Family for additional information. Table for additional S29CD-J_CL-J_00_B2 March 7, 2007 ...
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... S29CD-J & S29CL-J Flash Family for more on the Toggle Bit Algorithm. and DQ2 toggles, does not toggle. toggles, also toggles. ...
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... Figure 8.8 Toggle Bit Algorithm START Read Byte (DQ0-DQ7) Address = VA (Note 1) Read Byte (DQ0-DQ7) Address = VA No DQ6 = Toggle? Yes No DQ5 = 1? Yes Read Byte Twice (DQ0-DQ7) (Notes 1, 2) Adrdess = VA No DQ6 = Toggle? Yes FAIL S29CD-J & S29CL-J Flash Family PASS S29CD-J_CL-J_00_B2 March 7, 2007 ...
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... Table 8.9 Write Operation Status DQ7 (Note 2) DQ7# Toggle 0 Toggle 1 No toggle Data DQ7# Toggle for more information. for further details. S29CD-J & S29CL-J Flash Family (during Embedded Algorithms). The READY after the RH level since the output Figure 18.2, Figure 18.6, DQ5 DQ2 DQ6 ...
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... This section describes the various methods of protecting data stored in the memory array. An overview of these methods in shown Table 8.10 Reset Command Timing Description Figure 9.1. S29CD-J & S29CL-J Flash Family before it returns to the read or erase- Max. Unit 250 ns S29CD-J_CL-J_00_B2 March 7, 2007 ...
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... PPB N 5. PPBs programmed individually, but cleared collectively Sector Group Unprotected Sector Group Protected S29CD-J & S29CL-J Flash Family Persistent Method 1. Bit is volatile, and defaults to “0” on reset. 2. Programming to “1” locks all PPBs to their current state. 3. Once programmed to “1”, requires hardware reset to unlock ...
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... If the PPB Lock Bit is set, the PPB Program or erase command does not execute and times-out without programming or erasing the PPB 72. S29CD-J & S29CL-J Flash Family Section 20.1, S29CD-J_CL-J_00_B2 March 7, 2007 ...
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... OR wait 100 μs Write 0x48 to SG+WP Read from SG+WP NO DQ0 = 1? YES Done S29CD-J & S29CL-J Flash Family Note: Reads from the small bank at this point return the status of the operation, not read array data. YES 43 ...
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... OR wait 20 ms Write 0x40 to WP Read from WP NO DQ0 = 0? YES Done S29CD-J & S29CL-J Flash Family Note: Reads from the small bank at this point return the status of the operation, not read array data. YES S29CD-J_CL-J_00_B2 March 7, 2007 ...
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... Table 9.1 Sector Protection Schemes 0 Unprotected—PPB and DYB are changeable 1 Unprotected—PPB not changeable, DYB is changeable 0 0 Protected—PPB and DYB are changeable Protected—PPB not changeable, DYB is changeable 1 S29CD-J & S29CL-J Flash Family Sector State 45 ...
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... CC IO and V attain the operating voltages, deassertion of RESET CE while OE logical one (V IL S29CD-J & S29CL-J Flash Family on the WP# pin, the The system must provide the LKO is greater than LKO is ...
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... March 7, 2007 S29CD-J_CL-J_00_B2 Table 10.1 Secured Silicon Sector Addresses Sector Size (Bytes) 256 256 S29CD-J & S29CL-J Flash Family Table 10.1 for the Address Range 00000h-0003Fh (16 Mb & 32 Mb) FFFC0h–FFFFFh (32 Mb) 7FFC0h–7FFFFh (16 Mb) ...
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... Table 20.2, Sector Protection Command Definitions for address and data requirements for both command sequences. Table 10.1, Secured Silicon Sector Addresses on page ) for read access before it is ready to read data. If the CE S29CD-J & S29CL-J Flash Family Table 20.1, Memory 47. CC represents the standby current ...
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... V, the standby current is greater. and V power up is required to guarantee proper device initialization output from the device is disabled. The outputs are placed in the high IH S29CD-J & S29CL-J Flash Family for further discussion of the represents the automatic sleep mode ). If RESET# is held at CC4 49 ...
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... Electrical Specifications 13.1 Absolute Maximum Ratings Storage Temperature, Plastic Packages Ambient Temperature with Power Applied (Note 1) for 2.6 V devices (S29CD- (Note 1) for 3.3 V devices (S29CL- ACC, A9, and RESET# (Note 2) Address, Data, Control Signals (Note 1) Output Short Circuit Current (Note 3) Notes 1. Minimum DC voltage on input or I/O pins is – ...
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... CC CC March 7, 2007 S29CD-J_CL-J_00_B2 Table 14.1 Operating Ranges Parameter Industrial Devices ) A Extended Devices V for 2.6 V regulated voltage range (S29CD-J devices for 3.3 V regulated voltage range (S29CL-J devices (S29CD-J devices (S29CL-J devices) IO Test Conditions ...
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... Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 1000 1500 2000 Time in ns Figure 15.2 Typical I vs. Frequency CC1 2 3 Frequency in MHz S29CD-J & S29CL-J Flash Family 2500 3000 3500 4000 2 S29CD-J_CL-J_00_B2 March 7, 2007 5 ...
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... Table 17.2 Key to Switching Waveforms Inputs Changing from Changing from Don’t Care, Any Change Permitted Does Not Apply Figure 17.1 Input Waveforms and Measurement Levels Measurement Level IO S29CD-J & S29CL-J Flash Family C L All Options 1 TTL gate 30 5 0.0 V – ...
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... Table 18.1 V and V Power- Description V Setup Time CC V Setup Time IO RESET# Low Hold Time Figure 18.1 V and V Power-up Diagram VCS t VIOS t RSTH S29CD-J & S29CL-J Flash Family Test Setup Speed Unit Min 50 µs Min 50 µs Min 50 µs S29CD-J_CL-J_00_B2 March 7, 2007 ...
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... Max Read Min Toggle and Min Data# Polling Min Figure 18.2 Conventional Read Operations Timings t RC Addresses Stable t ACC OEH t CE High Z S29CD-J & S29CL-J Flash Family Speed Options 75MHz 66MHz 56MHz 40MHz 0J/ ...
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... Table 18.5 for write timing parameters Figure 18.3 Asynchronous Command Write Timing t CS Stable Address t WC Valid Data WEH t OEP S29CD-J & S29CL-J Flash Family S29CD-J_CL-J_00_B2 March 7, 2007 ...
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... Max (Note 2) Min Max Min Max Max Max Min Min Max Min (Note 2) Max (Note 2) Max Min (Note 1) Max Min (Note 2) Max Min Min S29CD-J & S29CL-J Flash Family Speed Options 66MHz, 56MHz, 40MHz 0J/ 1.5 7.5 8.5 9.5 10 ...
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... Figure 18.5 Synchronous Command Write/Read Timing t CES t ADVCS t ADVP t AS Valid Address Valid Address ADVCH Data In t WADVH2 t WADVH1 S29CD-J & S29CL-J Flash Family t CEZ OEZ t INDS t INDH t EHQZ Data Out S29CD-J_CL-J_00_B2 March 7, 2007 ...
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... Table 18.4 Hardware Reset (RESET#) Description Figure 18.6 RESET# Timings Ready Reset Timing to Bank NOT Executing Embedded Algorithm Reset Timing to Bank Executing Embedded Algorithm t Ready t RP S29CD-J & S29CL-J Flash Family Test All Speed Setup Options Unit Max 11 µs Max 500 ns Max 500 ns ...
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... Setup Time (Note 1) CC Recovery Time from RY/BY# (Note 1) RY/BY# Delay After WE# Rising Edge (Note 1) WP# Setup to WE# Rising Edge with Command WP# Hold after RY/BY# Rising Edge (Note 1) for more information. S29CD-J & S29CL-J Flash Family BUSY t WPRH All Speed Options Unit Min ...
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... Figure 18.8 Program Operation Timings WPH BUSY is the true data at the program address. S29CD-J & S29CL-J Flash Family Read Status Data (last two cycles WHWH1 Status D OUT ...
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... RC Valid RA t ACC OEH GHWL t WPH Valid Out t SR/W Read Cycle S29CD-J & S29CL-J Flash Family Read Status Data WHWH2 In Complete Progress Valid PA Valid PA t CPH t CP Valid Valid In In CE# Controlled Write Cycles ...
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... Complement Status Data Status Data ACC Valid Status Valid Status (first read) (second read) S29CD-J & S29CL-J Flash Family High Z Valid Data True High Z Valid Data True VA VA Valid Status Valid Data (stops toggling) 63 ...
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... Erase Enter Erase Suspend Program Erase Suspend Erase Suspend Read Program t OE Status Data S29CD-J & S29CL-J Flash Family Erase Resume Erase Suspend Erase Read Status Data S29CD-J_CL-J_00_B2 March 7, 2007 Erase ...
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... Command for sector protect verify is 48h. Command for sector unprotect verify is 40h. March 7, 2007 S29CD-J_CL-J_00_B2 Valid* 60h/68h** Sector Protect: 150 µs Sector Unprotect S29CD-J & S29CL-J Flash Family Valid* Valid* Verify 40h/48h*** Status 65 ...
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... WE# Hold Time WE# Width CE# Pulse Width CE# Pulse Width High Programming Operation (Note 2) Sector Erase Operation (Note 2) WE# Rising Edge Setup to ADV# Falling Edge WE# Rising Edge Setup to CLK Rising Edge for more information. S29CD-J & S29CL-J Flash Family All Speed Options Min 65 Min 0 Min 45 ...
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... WPH GHEL t t WHWH1 CPH t BUSY for program PD for program 55 for erase 30 for sector erase 10 for chip erase S29CD-J & S29CL-J Flash Family Data# Polling PA DQ7# D OUT = data written to the device. OUT 67 ...
Page 68
... C, 2 100K cycles. Additionally, programming typicals assume checkerboard CC Table 18.8 PQFP and Fortified BGA Pin Capacitance Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance S29CD-J & S29CL-J Flash Family Comments s Excludes 00h programming prior to erasure (Note 4) s µs µs Excludes system level overhead ...
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... Max. timeout for word/doubleword program 2 0000h Max. timeout for buffer write 2 0007h Max. timeout per individual block erase 2 0000h Max. timeout for full chip erase 2 S29CD-J & S29CL-J Flash Family 19.3. In order to terminate reading CFI Table 19.1-Table Description Description pin present) PP pin present) ...
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... Erase Suspend (1 byte Not Supported 0002h Read Only Read and Write Sector Protect (1 byte) 0001h 00 = Not Supported Number of sectors in per group Temporary Sector Unprotect 0000h 00h = Not Supported, 01h = Supported S29CD-J & S29CL-J Flash Family Description N Description S29CD-J_CL-J_00_B2 March 7, 2007 ...
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... If data at 4Ah is zero XX = Number of banks Bank 1 Region Information (1 byte) 0017h XX = Number of Sectors in Bank 1 Bank 2 Region Information (1 byte) 0037h XX = Number of Sectors in Bank 2 Bank 3 Region Information (1 byte) 0000h XX = Number of Sectors in Bank 3 Bank 4 Region Information (1 byte) 0000h XX = Number of Sectors in Bank 4 S29CD-J & S29CL-J Flash Family Description 71 ...
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... Command is ignored during any Embedded Program, Embedded Erase, or Suspend operation. 18. The Unlock Bypass Entry command is required prior to any Unlock Bypass operation. The Unlock Bypass Reset command is required to return to the read mode. S29CD-J & S29CL-J Flash Family Fourth Fifth Sixth Addr Data ...
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... PPBs. 11. In the fourth cycle, 00h indicates PPB set; 01h indicates PPB not set. 12. The status of additional PPBs and DYBs may be read (following the fourth cycle) without reissuing the entire command sequence. S29CD-J & S29CL-J Flash Family Fourth Fifth Sixth ...
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... OEH WEH WPH and t from figure. WADVH WCKS BUSY (OE# High Pulse) OEP from table. Added t and t OES WADVS S29CD-J & S29CL-J Flash Family Ratings to reflect 16 Mb & Changed CLKH OEP WCKS S29CD-J_CL-J_00_B2 March 7, 2007 . CLKL ...
Page 75
... Changed cycling endurance specification to typical. Performance Characteristics Changed t Ordering Information Added quantities to packing type descriptions, restructured table for easier reference. S29CD-J & S29CL-J Flash Family Autoselect Codes (High Voltage In table, modified description of read cycle 3 DQ7–DQ0. Method) DQ6 and DQ2 Indications In table, corrected third column heading Section 8 ...
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... Description test conditions and I maximum specification. CCB CC1 . L RC and t specifications to table. WEH OEP S29CD-J & S29CL-J Flash Family , for 75 MHz device. ACC and t INDS CLKL AAVH WADVH1 S29CD-J_CL-J_00_B2 March 7, 2007 ...
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... Copyright © 2005–2007 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners. March 7, 2007 S29CD-J_CL-J_00_B2 S29CD-J & S29CL-J Flash Family 77 ...