s29cd-j Meet Spansion Inc., s29cd-j Datasheet - Page 25

• Manufacturer Part Number: s29cd-j
• Description: 32/16 Megabit Cmos 2.6 Volt Or 3.3 Volt-only Simultaneous Read/write, Dual Boot, Burst Mode Flash Memory With Versatilei/o?
• Manufacturer: Meet Spansion Inc.

March 7, 2007 S29CD-J_CL-J_00_B2
8.4.1
2-, 4-, 8- Double Word Linear Burst Operation
Like the main memory access, the Secured Silicon Sector memory is accessed with the same burst or
asynchronous timing as defined in the Configuration Register. However, the user must recognize burst
operations past the 256 byte Secured Silicon boundary returns invalid data.
Burst read operations occur only to the main flash memory arrays. The Configuration Register and protection
bits are treated as single cycle reads, even when burst mode is enabled. Read operations to these locations
results in the data remaining valid while OE# is at V
device.
In a linear burst read operation, a fixed number of words (2, 4, or 8 double words) are read from consecutive
addresses that are determined by the group within which the starting address falls. Note that 1 double word =
32 bits. See
The IND/WAIT# signal, or End of Burst Indicator signal, transitions active (V
in a linear burst read before a wrap around. This transition indicates that the system should initiate another
ADV# to start the next burst access. If the system continues to clock the device, the next access wraps
around to the starting address of the previous burst access. The IND/WAIT# signal is floating when not active.
Notes
1. The default configuration in the Control Register for Bit 6 is “1,” indicating that the device delivers data on the rising edge of the CLK
2. The device is capable of holding data for one CLK cycle.
3. If RESET# is asserted low during a burst access, the burst access is immediately terminated and the device defaults back to
4. CE# must meet the required burst read setup times for burst cycle initiation. If CE# is taken to V
5. Restarting a burst cycle is accomplished by taking CE# and ADV# to V
6. A burst access is initiated and the address is latched on the first rising CLK edge when ADV# is active or upon a rising ADV# edge,
7. The OE# (Output Enable) pin is used to enable the linear burst data on the DQ data bus pin. De-asserting the OE# pin to V
8. Halting the burst sequence is accomplished by either taking CE# to V
The IND/WAIT# signal is controlled by the OE# signal. If OE# is at V
driven. If OE# is at V
the burst sequence.
IND/WAIT# timing. See
signal.
asynchronous read mode. When this happens, the DQ data bus signal floats and the Configuration Register contents are reset to their
default conditions.
burst cycle, the device immediately exits the burst sequence and floats the DQ bus signal.
whichever occurs first. If the ADV# signal is taken to VIL prior to the end of a linear burst sequence, the previous address is discarded and
subsequent burst transfers are invalid. A new burst is initiated when ADV# transitions back to V
burst operation floats the data bus, but the device continues to operate internally as if the burst sequence continues until the linear burst
is complete. The OE# pin does not halt the burst sequence, The DQ bus remains in the float state until OE# is taken to V
D a t a
Table 8.2
Eight Linear Data Transfers
Four Linear Data Transfers
Two Linear Data Transfers
Data Transfer Sequence
Table 8.3
IL
S h e e t
, the IND/ WAIT# signal is driven at V
for all valid burst output sequences.
Figure 8.3
S29CD-J & S29CL-J Flash Family
lists the valid combinations of the Configuration Register bits that impact the
Table 8.2 32-Bit Linear and Burst Data Order
( P r e l i m i n a r y )
for the IND/WAIT# timing diagram.
IL
, regardless of the number of CLK cycles applied to the
IH
IL
or re-issuing a new ADV# pulse.
.
IH
until it transitions to V
IH
1-2-3-4-5-6-7-0 (A1:A-1/A2-A0 = 001)
2-3-4-5-6-7-0-1 (A1:A-1/A2-A0 = 010)
3-4-5-6-7-0-1-2 (A1:A-1/A2-A0 = 011)
4-5-6-7-0-1-2-3 (A1:A-1/A2-A0 = 100)
5-6-7-0-1-2-3-4 (A1:A-1/A2-A0 = 101)
6-7-0-1-2-3-4-5 (A1:A-1/A2-A0 = 110)
7-0-1-2-3-4-5-6 (A1:A-1/A2-A0 = 111)
0-1-2-3-4-5-6-7 (A1:A-1A2-A0 = 000)
, the IND/WAIT# signal floats and is not
(Initial Access Address, x16)
0-1-2-3 (A0:A-1/A1-A0 = 00)
1-2-3-0 (A0:A-1/A1-A0 = 01)
3-0-1-2 (A0:A-1/A1-A0 = 11)
2-3-0-1 (A:A-1/A1-A0 = 10)
Output Data Sequence
IL
IH
) during the last transfer of data
IH
before a clock edge.
at any time during the burst linear or
0-1 (A0 = 0)
1-0 (A0 = 1)
IL
, indicating the end of
IL
.
IH
during a
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