s29cd-j Meet Spansion Inc., s29cd-j Datasheet - Page 23

• Manufacturer Part Number: s29cd-j
• Description: 32/16 Megabit Cmos 2.6 Volt Or 3.3 Volt-only Simultaneous Read/write, Dual Boot, Burst Mode Flash Memory With Versatilei/o?
• Manufacturer: Meet Spansion Inc.

8.2
8.3
March 7, 2007 S29CD-J_CL-J_00_B2
Asynchronous Read
Hardware Reset (RESET#)
All memories require access time to output array data. In an asynchronous read operation, data is read from
one memory location at a time. Addresses are presented to the device in random order, and the propagation
delay through the device causes the data on its outputs to arrive asynchronously with the address on its
inputs.
The internal state machine is set for asynchronously reading array data upon device power-up, or after a
hardware reset. This ensures that no spurious alteration of the memory content occurs during the power
transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles
that assert valid addresses on the device address inputs produce valid data on the device data outputs. The
device remains enabled for read access until the command register contents are altered.
The device has two control functions which must be satisfied in order to obtain data at the outputs. CE# is the
power control and should be used for device selection (CE# must be set to V
output control and should be used to gate data to the output pins if the device is selected (OE# must be set to
V
Address access time (t
access time (t
output enable access time (t
(assuming the addresses have been stable for at least a period of t
least t
Note
Operation is shown for the 32-bit data bus. For the 16-bit data bus, A-1 is required.
Refer to
Conventional Read Operations Timings on page 55
Characteristics table represents the active current specification for reading array data.
The RESET# pin is an active low signal that is used to reset the device under any circumstances. A logic “0”
on this input forces the device out of any mode that is currently executing back to the reset state. RESET#
may be tied to the system reset circuitry. A system reset would thus also reset the device. To avoid a potential
bus contention during a system reset, the device is isolated from the DQ data bus by tristating the data
outputs for the duration of the RESET pulse. All data outputs are “don’t care” during the reset operation.
If RESET# is asserted during a program or erase operation, the RY/BY# output remains low until the reset
operation is internally complete. The RY/BY# pin can be used to determine when the reset operation is
complete. Since the device offers simultaneous read/write operation, the host system may read a bank after a
period of t
IND/WAIT#
Addresses
IL
in order to read data). WE# should remain at V
CE
ADV#
Data
WE#
CE#
CLK
OE#
-t
Section 18.2, Asynchronous Operations on page 55
OE
READY2
D a t a
time).
CE
Float
V
) is the delay from the stable addresses and stable CE# to valid data at the output pins. The
Address 0
IH
, if the bank was in the read/reset mode at the time RESET# was asserted. If one of the
Figure 8.1
S h e e t
ACC
) is equal to the delay from stable addresses to valid output data. The chip enable
OE
V
Address 1
S29CD-J & S29CL-J Flash Family
OH
shows the timing diagram of an asynchronous read operation.
) is the delay from the falling edge of OE# to valid data at the output pins
D0
Figure 8.1 Asynchronous Read Operation
( P r e l i m i n a r y )
Address 2
D1
IH
for another timing diagram. I
(when reading data).
Address 3
D2
for timing specifications and to
ACC
-t
OE
and CE# has been asserted for at
IL
D3
to read data). OE# is the
CC1
in the DC
Figure 18.2,
D3
Float
23