s29cd-j Meet Spansion Inc., s29cd-j Datasheet - Page 49

• Manufacturer Part Number: s29cd-j
• Description: 32/16 Megabit Cmos 2.6 Volt Or 3.3 Volt-only Simultaneous Read/write, Dual Boot, Burst Mode Flash Memory With Versatilei/o?
• Manufacturer: Meet Spansion Inc.

12.2
12.3
12.4
March 7, 2007 S29CD-J_CL-J_00_B2
Automatic Sleep Mode
Hardware RESET# Input Operation
Output Disable (OE#)
Caution
Entering standby mode via the RESET# pin also resets the device to read mode and floats the data I/O pins.
Furthermore, entering I
locations being operated on at the time of the RESET# pulse. These locations require updating after the
device resumes standard operations. See
RESET# pin and its functions.
The automatic sleep mode minimizes Flash device energy consumption. The automatic sleep mode is
independent of the CE#, WE# and OE# control signals. While in sleep mode, output data is latched and
always available to the system.
While in asynchronous mode, the device automatically enables this mode when addresses remain stable for
t
synchronous mode, the device automatically enables this mode when either the first active CLK level is
greater than t
I
current specification.
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET#
is driven low, the device immediately terminates any operation in progress, tristates all outputs, resets the
configuration register, and ignores all read/write commands for the duration of the RESET# pulse. The device
also resets the internal state machine to reading array data. Any operation that was interrupted should be
reinitiated once the device is ready to accept another command sequence, in order to ensure data integrity.
When RESET# is held at V
V
RESET# may be tied to the system reset circuitry, thus a system reset would also reset the Flash memory,
enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains low until the reset
operation is internally complete. This action requires between 1 µs and 7 µs for either Chip Erase or Sector
Erase. The RY/BY# pin can be used to determine whether the reset operation is complete. Otherwise, allow
for the maximum reset time of 11 µs.
If RESET# is asserted when a program or erase operation is not executing (RY/BY# = 1), the reset operation
completes within 500 ns. The Simultaneous Read/Write feature of this device allows the user to read a bank
after 500 ns if the bank is in the read/reset mode at the time RESET# is asserted. If one of the banks is in the
middle of either a program or erase operation when RESET# is asserted, the user must wait 11 µs before
accessing that bank.
Asserting RESET# active during V
until V
When the OE# input is at V
impedance state.
ACC
CC8
IL
but not within V
in
+ 60 ns. Standard address access timings provide new data when addresses are changed. While in
CC
Section 15.1, DC Characteristic, CMOS Compatible on page 51
and V
D a t a
ACC
IO
or the CLK runs slower than 5 MHz. A new burst operation is required to provide new data.
have reached steady state voltages.
SS
S h e e t
±0.2 V, the standby current is greater.
CC7
SS
during a program or erase operation leaves erroneous data in the address
IH
, output from the device is disabled. The outputs are placed in the high
S29CD-J & S29CL-J Flash Family
±0.2 V, the device draws CMOS standby current (I
( P r e l i m i n a r y )
CC
and V
Hardware RESET# Input Operation
IO
power up is required to guarantee proper device initialization
represents the automatic sleep mode
for further discussion of the
CC4
). If RESET# is held at
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