scan25100-evk National Semiconductor Corporation, scan25100-evk Datasheet

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scan25100-evk

Manufacturer Part Number
scan25100-evk
Description
2457.6, 1228.8, And 614.4 Mbps Cpri Serdes With Auto Re Sync And Precision Delay Calibration Measurement
Manufacturer
National Semiconductor Corporation
Datasheet
© 2006 National Semiconductor Corporation
SCAN25100
2457.6, 1228.8, and 614.4 Mbps CPRI SerDes with Auto RE
Sync and Precision Delay Calibration Measurement
General Description
The SCAN25100 is a 2457.6, 1228.8, and 614.4 Mbps seri-
alizer/deseralizer (SerDes) for high-speed bidirectional serial
data transmission over FR-4 printed circuit board backplanes,
balanced cables, and optical fiber. The SCAN25100 inte-
grates precision delay calibration measurement (DCM) cir-
cuitry that measures link delay components to better than ±
800 ps accuracy.
The SCAN25100 features independent transmit and receive
PLLs, on-chip oscillator, and intelligent clock management
circuitry to automatically perform remote radio head synchro-
nization and reduce the cost and complexity of external clock
networks.
The SCAN25100 is programmable though an MDIO interface
as well as through pins, featuring configurable transmitter de-
emphasis, receiver equalization, speed rate selection, inter-
nal pattern generation/verification, and loop back modes. In
addition to at-speed BIST, the SCAN25100 includes IEEE
1149.1 and 1149.6 testability.
Note: For a full datasheet of the SCAN25100 please con-
tact your local National Semiconductor representitive.
Features
Block Diagram
Exceeds LV and HV CPRI voltage and jitter requirements
2457.6, 1228.8, and 614.4 Mbps operation
Integrated delay calibration measurement (DCM) directly
measures T14 and Toffset delays to
201834
± 800 ps
DCM also measures chip and other delays to
accuracy
Deterministic chip latency
Automatic receiver lock and RE synchronization without
reference clock or external crystal
Independent transmit and receive PLLs for seamless RE
synchronization
Low noise recovered clock output
Requires no jitter cleaning in single-hop applications
>8 kV ESD on the CML IO, >7 kV on all other pins, >2 kV
CDM
Hot plug protection
LOS, LOF, 8b/10b line code violation, comma, and
receiver PLL lock reporting
Programmable hyperframe length and start of hyperframe
character
Programmable transmit de-emphasis and receive
equalization with on-chip termination
Advanced testability features
— IEEE 1149.1 and 1149.6
— At-speed BIST pattern generator/verifier
— Multiple loopback modes
1.8V or 3.3V compatible parallel bus interface
100-pin TQFP package with exposed dap
Industrial –40 to +85° C temperature range
20183442
November 2006
www.national.com
± 1200 ps

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scan25100-evk Summary of contents

Page 1

... In addition to at-speed BIST, the SCAN25100 includes IEEE 1149.1 and 1149.6 testability. Note: For a full datasheet of the SCAN25100 please con- tact your local National Semiconductor representitive. Features ■ ...

Page 2

... Pin Diagram www.national.com SCAN25100 (Top View) 100–Pin TQFP with Exposed Ground Pad Order Number SCAN25100TYA See NS Number VXF100B 2 20183402 ...

Page 3

Pin Descriptions Pin # Pin Name I/O, Type HIGH SPEED DIFFERENTIAL I/O 12 DOUTP O, CML 11 DOUTN 18 RINP I, CML 17 RINN PARALLEL DATA BUS 65 DIN [0] I, LVTTL or 1.8V 66 DIN [1] LVCMOS Internal 67 ...

Page 4

Pin # Pin Name I/O, Type 79 CDET O, LVTTL or 1.8V LVCMOS CONTROL PINS 82 PE [0] I, LVTTL or 1. [1] LVCMOS Internal pull down 88 EQ [0] I, LVTTL or 1. [1] LVCMOS ...

Page 5

Pin # Pin Name I/O, Type 96 SPMODE [0] I, LVTTL or 1.8V 97 SPMODE [1] LVCMOS Internal pull down 98 TENBMODE I, LVTTL or 1.8V LVCMOS, Internal pull down 99 LOOP [0] I, LVTTL or 1.8V 100 LOOP [1] ...

Page 6

Pin # Pin Name I/O, Type GROUND DAP 101 GND I, Ground Note: I= input O = output Internal pull down = input pin is pulled low by an internal resistor resistor www.national.com Description Device ground. Pad must be soldered ...

Page 7

... Soldering, 10–20 sec Lead-free +260°C flow is available Maximum Package Power Dissipation at 25°C 100-pin TQFP with Exposed Pad Note: This is the maximum TQFP-100 package power dissipation capability. For SCAN25100 power dissipation, see the information in the Electrical Characteristics section. Electrical Characteristics Symbol Parameter LVCMOS DC SPECIFICATIONS (1 ...

Page 8

Symbol Parameter V Low level output voltage OL C Input/Output Capacitance IO MDIO/MDC/ADD0-4 DC SPECIFICATIONS V High level input voltage IH V Low level input voltage IL I Input Current IN V High level output voltage OH V Low level ...

Page 9

Symbol Parameter R Differential Input Terminations R RLR Input Return Loss (Note 12 Receive latency LAT-R (Notes 10, 8) JIT Total input jitter tolerance (Note 12) Input CJPAT with BER of 10 R-TOL F Receiver lock range R-LOCK ...

Page 10

... Note 14: Serial side DCM readings are referenced to the first bit of the K28.5 pattern {110000 0101 001111 1010}. Parallel side DCM readings are referenced to the TXCLK or RXCLK edge (not the data edge) that registers the K character as an input or output. Note 15: DCM readings have been validated when the RXCLK pin on the SCAN25100 is used as an output in "WRITE" mode (RXCLKMODE = 0) and IOVDD = 3.3V. ...

Page 11

AC Timing Diagrams READ MODE 20183409 WRITE MODE 20183410 11 www.national.com ...

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... Physical Dimensions See www.national.com/quality/marking_conventions.html for additional part marking information www.national.com inches (millimeters) unless otherwise noted 100-Pin TQFP with Exposed Ground Pad (Top View) Order Number SCAN25100TYA NS Package Number VXF100B 12 ...

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Notes 13 www.national.com ...

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... National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. ...

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