scan25100-evk National Semiconductor Corporation, scan25100-evk Datasheet - Page 3

• Manufacturer Part Number: scan25100-evk
• Description: 2457.6, 1228.8, And 614.4 Mbps Cpri Serdes With Auto Re Sync And Precision Delay Calibration Measurement
• Manufacturer: National Semiconductor Corporation

HIGH SPEED DIFFERENTIAL I/O
PARALLEL DATA BUS
CLOCK SIGNALS
LINE STATUS
Pin Descriptions
Pin #
12
11
18
17
65
66
67
68
69
70
71
72
73
74
53
54
55
56
57
58
59
60
61
62
64
52
22
23
78
77
6
7
DOUTP
DOUTN
RINP
RINN
DIN [0]
DIN [1]
DIN [2]
DIN [3]
DIN [4]
DIN [5]
DIN [6]
DIN [7]
DIN [8]
DIN [9]
ROUT [0]
ROUT [1]
ROUT [2]
ROUT [3]
ROUT [4]
ROUT [5]
ROUT [6]
ROUT [7]
ROUT [8]
ROUT [9]
REFCLKP
REFCLKN
TXCLK
RXCLK
SYSCLKP
SYSCLKN
LOS
LOCKB
Pin Name
I/O, LVTTL or 1.8V
LVCMOS Internal
O, LVTTL or 1.8V
LVCMOS Internal
LVCMOS Internal
O, LVTTL or 1.8V
O, LVTTL or 1.8V
I, LVTTL or 1.8V
I, LVTTL or 1.8V
I, LVDS or
I/O, Type
pull down
pull down
pull down
LVCMOS
LVCMOS
LVCMOS
O, LVDS
LVPECL
O, CML
I, CML
Inverting and non-inverting high speed CML differential outputs of the serializer. On-
chip termination resistors connect from DO+ and DO− to an internal reference
Inverting and non-inverting high speed differential inputs of the deseralizer. On-chip
termination resistors connect from RI+ and RI− to an internal reference. On-chip
termination resistors are configured for AC-coupled applications.
Transmit data word.
In 10-bit mode, the 10-bit code-group at DIN [0–9] is serialized with the internal 8b/
10b encoder disabled. Bit 9 is the msb.
The 8B/10B specification is defined in IEEE 802.3-2000 section 36.2.2
Deserialized receive data word.
In 10-bit mode, ROUT [0-9] is the deserialized received data word in 10-bit code group.
Bit 9 is the msb.
The 8B/10B specification is defined in IEEE 802.3-2000 section 36.2.2
Inverting and non-inverting differential serializer reference clock. A low jitter clock
source should be connected to REFCLKP & REFCLKN.
Transmit clock. TXCLK must be synchronous to REFCLK to avoid FIFO under/
overflow though it may differ in phase.
Write mode: RXCLK is a recovered clock output pin.
Read mode: RXCLK is an input pin. ROUT [9:0] are latched out on RXCLK rising and
falling edges. RXCLK must be synchronous to the incoming serial data to avoid FIFO
over/underflow, though it may differ in phase. See RXCLKMODE pin description for
more details.
30.72 MHz output clock. (OPMODE must be low.)
Receiver CPRI loss of signal (LOS) status (8-bit mode only).
0 = signal detected (per CPRI standard)
1 = signal lost (per CPRI standard)
See “LOS Detection” under “Functional Description” for more details.
Receiver PLL lock status
0 = Receiver PLL locked
1 = Receiver PLL not locked
3
Description
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