scan25100-evk National Semiconductor Corporation, scan25100-evk Datasheet - Page 10

• Manufacturer Part Number: scan25100-evk
• Description: 2457.6, 1228.8, And 614.4 Mbps Cpri Serdes With Auto Re Sync And Precision Delay Calibration Measurement
• Manufacturer: National Semiconductor Corporation

www.national.com
t
t
t
t
MINIMUM PULSE WIDTH, Hardware Reset (Note 13)
t
t
t
JTAG TIMING SPECIFICATIONS
f
t
t
t
t
t
t
t
t
t
DELAY CALIBRATION MEASUREMENT (DCM) (Notes 12, 14, 15)
T
T
T
T
T
T
S-MDIO
H-MDIO
D-MDIO
X-MDIO
TX-RST
RX-RST
RST
JTAG
R-J
F-J
S-TDI
H-TDI
S-TMS
H-TMS
W-TCK
W-TRST
REC
14
offset
ser
des
in-out
out-in
Symbol
Note 1: “Absolute Maximum Ratings” are the ratings beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits.
Note 2: Typical parameters are measured at nominal supply levels and T
Note 3: Transmit Jitter testing methodology is defined in Appendix 48B of IEEE 802.2ae-2002. The SCAN25100 transmit output jitter is constant for all valid CPRI
datarates. For 614.4 and 1228.8 Mbps rates, the transmit jitter is significantly less then the specified limits in terms of UI.
Note 4: CJPAT is a stress pattern defined in IEEE 802.2ae-2002 Appendix 48A
Note 5: CDET nominal valid duration is determined by the CPRI data rate. CDET timing is similar to the ROUT[0:9] timing.
Note 6: Transmit or Receive K28.5 pattern. Assumes TXCLK is stable and toggles only after all SerDes clocks become synchronous.
Note 7: Transmit latency is fixed once the link is established and is guaranteed by the Tser specification.
Note 8: Receive latency is fixed once the link is established and is guaranteed by the Tdes specification.
Note 9: Conditions: The TX PLL is locked, the TXCLK is stable and the TXCLK is synchronous.
Note 10: Conditions: The RX PLL is locked to the incoming data and the SCAN25100 is in WRITE mode.
Note 11: Receiver output timing specifications for TS-R and TH-R are tested at the CPRI rate of 2.4576 Gbps.
Note 12: Limits are guaranteed by design and characterization over process, supply voltage, and temperature variations.
Note 13: Limits are guaranteed by design.
Note 14: Serial side DCM readings are referenced to the first bit of the K28.5 pattern {110000 0101 001111 1010}. Parallel side DCM readings are referenced
to the TXCLK or RXCLK edge (not the data edge) that registers the K character as an input or output.
Note 15: DCM readings have been validated when the RXCLK pin on the SCAN25100 is used as an output in "WRITE" mode (RXCLKMODE = 0) and IOVDD
= 3.3V.
Note 16: Edge rate characterization includes the loading effects of 1.0 uF AC-coupling capacitors and 4 inches of 100-Ohm differential microstrip.
Setup Time
Hold Time
Delay Time
Transition Time
Transmiter Reset
Receiver Reset
SerDes Reset
JTAG TCK Frequency
TDO data transition time (20% to
80%)
Setup Time TDI to TCK High or Low
Hold Time TDI to TCK High or Low
Setup Time TMS to TCK High or
Low
Hold Time TMS to TCK High or Low
TCK Pulse Width
TRSTB Pulse Width
Recovery Time TRSTB to TCK
T
T
Serializer Delay Accuracy
Deserializer Delay Accuracy
T
T
14
offset
in-out
out-in
Delay Accuracy
Delay Accuracy
Delay Accuracy
Delay Accuracy
Parameter
MDIO (input) valid to MDC rising
clock
MDC rising edge to MDIO (input)
invalid
MDIO (output) delay from MDC
rising edge
Measured at MDIO when used as
output, CL = 470 pF
TXPWDNB = 0
RXPWDNB = 0
RESETB = 0
R
Receive and Transmit PLLs locked
to valid hyperframe data.
L
= 1000Ω, C
A
Condition
= 25°C. They are for reference purposes and are not production-tested.
L
10
= 15 pF
Min
2.5
10
10
25
10
14
0
2
2
2
2
(Note 2)
Typ
1
1
1
1
2
± 1200
± 1200
± 1200
± 1200
± 800
± 800
Max
300
Units
MHz
ns
ns
ns
ns
us
us
us
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps