s908gr16ag4cfj Freescale Semiconductor, Inc, s908gr16ag4cfj Datasheet - Page 182

• Manufacturer Part Number: s908gr16ag4cfj
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

System Integration Module (SIM)
15.5.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after
completion of the current instruction. When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the condition code register) and if the
corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is
serviced first.
is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the
LDA instruction is executed.
The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the
INT1 RTI prefetch, this is a redundant operation.
15.5.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the
interrupt mask (I bit) in the condition code register.
182
Figure 15-11
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
INT1
INT2
demonstrates what happens when two interrupts are pending. If an interrupt
Figure 15-11
CLI
LDA
PSHH
PULH
RTI
PSHH
PULH
RTI
MC68HC908GR16A Data Sheet, Rev. 1.0
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Interrupt Recognition Example
NOTE
NOTE
INT1 INTERRUPT SERVICE ROUTINE
INT2 INTERRUPT SERVICE ROUTINE
BACKGROUND
ROUTINE
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